
Leigh M. Garbowski
Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2764, 2825, 2763, 2768, 2304 |
| Total Applications | 1705 |
| Issued Applications | 1528 |
| Pending Applications | 70 |
| Abandoned Applications | 125 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 38592
[patent_doc_number] => 07788623
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-08-31
[patent_title] => 'Composite wire indexing for programmable logic devices'
[patent_app_type] => utility
[patent_app_number] => 11/947662
[patent_app_country] => US
[patent_app_date] => 2007-11-29
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/788/07788623.pdf
[firstpage_image] =>[orig_patent_app_number] => 11947662
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/947662 | Composite wire indexing for programmable logic devices | Nov 28, 2007 | Issued |
Array
(
[id] => 4940585
[patent_doc_number] => 20080077905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-27
[patent_title] => 'VIDEO PROCESSING ARCHITECTURE DEFINITION BY FUNCTION GRAPH METHODOLOGY'
[patent_app_type] => utility
[patent_app_number] => 11/942622
[patent_app_country] => US
[patent_app_date] => 2007-11-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/942622 | VIDEO PROCESSING ARCHITECTURE DEFINITION BY FUNCTION GRAPH METHODOLOGY | Nov 18, 2007 | Abandoned |
Array
(
[id] => 4558435
[patent_doc_number] => 07890892
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[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'Balanced and bi-directional bit line paths for memory arrays with programmable memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/940542
[patent_app_country] => US
[patent_app_date] => 2007-11-15
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[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/940542 | Balanced and bi-directional bit line paths for memory arrays with programmable memory cells | Nov 14, 2007 | Issued |
Array
(
[id] => 5332892
[patent_doc_number] => 20090113369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 11/932062
[patent_app_country] => US
[patent_app_date] => 2007-10-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932062 | Registry for electronic design automation of integrated circuits | Oct 30, 2007 | Issued |
Array
(
[id] => 5332890
[patent_doc_number] => 20090113367
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[patent_issue_date] => 2009-04-30
[patent_title] => 'ANALOG IC PLACEMENT USING SYMMETRY-ISLANDS'
[patent_app_type] => utility
[patent_app_number] => 11/930992
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[patent_app_date] => 2007-10-31
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[firstpage_image] =>[orig_patent_app_number] => 11930992
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/930992 | Analog IC placement using symmetry-islands | Oct 30, 2007 | Issued |
Array
(
[id] => 4621777
[patent_doc_number] => 08001508
[patent_country] => US
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[patent_issue_date] => 2011-08-16
[patent_title] => 'Method and system for analyzing input/output simultaneous switching noise'
[patent_app_type] => utility
[patent_app_number] => 11/877072
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[pdf_file] => patents/08/001/08001508.pdf
[firstpage_image] =>[orig_patent_app_number] => 11877072
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/877072 | Method and system for analyzing input/output simultaneous switching noise | Oct 22, 2007 | Issued |
Array
(
[id] => 9112
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[patent_title] => 'Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/876062 | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates | Oct 21, 2007 | Issued |
Array
(
[id] => 5582814
[patent_doc_number] => 20090102016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/876402
[patent_app_country] => US
[patent_app_date] => 2007-10-22
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[pdf_file] => publications/A1/0102/20090102016.pdf
[firstpage_image] =>[orig_patent_app_number] => 11876402
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/876402 | DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES | Oct 21, 2007 | Abandoned |
Array
(
[id] => 5587522
[patent_doc_number] => 20090106724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design'
[patent_app_type] => utility
[patent_app_number] => 11/875032
[patent_app_country] => US
[patent_app_date] => 2007-10-19
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[pdf_file] => publications/A1/0106/20090106724.pdf
[firstpage_image] =>[orig_patent_app_number] => 11875032
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/875032 | Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design | Oct 18, 2007 | Issued |
Array
(
[id] => 7706531
[patent_doc_number] => 08091053
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'System, method, and program for generating circuit'
[patent_app_type] => utility
[patent_app_number] => 11/907712
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[firstpage_image] =>[orig_patent_app_number] => 11907712
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907712 | System, method, and program for generating circuit | Oct 15, 2007 | Issued |
Array
(
[id] => 5286718
[patent_doc_number] => 20090100393
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[patent_issue_date] => 2009-04-16
[patent_title] => 'METHOD AND APPARATUS FOR INCREMENTALLY COMPUTING CRITICALITY AND YIELD GRADIENT'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/870672 | Method and apparatus for incrementally computing criticality and yield gradient | Oct 10, 2007 | Issued |
Array
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[id] => 5442929
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[patent_title] => 'Validation Of An Integrated Circuit For Electro Static Discharge Compliance'
[patent_app_type] => utility
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Array
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863512 | Synthesis of assertions from statements of power intent | Sep 27, 2007 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861492 | Method for fabricating a semiconductor device having an extended stress liner | Sep 25, 2007 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859162 | METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE AND SOFTWARE THEREFOR | Sep 20, 2007 | Abandoned |