Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 38592 [patent_doc_number] => 07788623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Composite wire indexing for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/947662 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788623.pdf [firstpage_image] =>[orig_patent_app_number] => 11947662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947662
Composite wire indexing for programmable logic devices Nov 28, 2007 Issued
Array ( [id] => 4940585 [patent_doc_number] => 20080077905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'VIDEO PROCESSING ARCHITECTURE DEFINITION BY FUNCTION GRAPH METHODOLOGY' [patent_app_type] => utility [patent_app_number] => 11/942622 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5485 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077905.pdf [firstpage_image] =>[orig_patent_app_number] => 11942622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942622
VIDEO PROCESSING ARCHITECTURE DEFINITION BY FUNCTION GRAPH METHODOLOGY Nov 18, 2007 Abandoned
Array ( [id] => 4558435 [patent_doc_number] => 07890892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Balanced and bi-directional bit line paths for memory arrays with programmable memory cells' [patent_app_type] => utility [patent_app_number] => 11/940542 [patent_app_country] => US [patent_app_date] => 2007-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7040 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890892.pdf [firstpage_image] =>[orig_patent_app_number] => 11940542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940542
Balanced and bi-directional bit line paths for memory arrays with programmable memory cells Nov 14, 2007 Issued
Array ( [id] => 5332892 [patent_doc_number] => 20090113369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/932062 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3895 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113369.pdf [firstpage_image] =>[orig_patent_app_number] => 11932062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932062
Registry for electronic design automation of integrated circuits Oct 30, 2007 Issued
Array ( [id] => 5332890 [patent_doc_number] => 20090113367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'ANALOG IC PLACEMENT USING SYMMETRY-ISLANDS' [patent_app_type] => utility [patent_app_number] => 11/930992 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8554 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113367.pdf [firstpage_image] =>[orig_patent_app_number] => 11930992 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/930992
Analog IC placement using symmetry-islands Oct 30, 2007 Issued
Array ( [id] => 4621777 [patent_doc_number] => 08001508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-16 [patent_title] => 'Method and system for analyzing input/output simultaneous switching noise' [patent_app_type] => utility [patent_app_number] => 11/877072 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 5841 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001508.pdf [firstpage_image] =>[orig_patent_app_number] => 11877072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877072
Method and system for analyzing input/output simultaneous switching noise Oct 22, 2007 Issued
Array ( [id] => 9112 [patent_doc_number] => 07818702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates' [patent_app_type] => utility [patent_app_number] => 11/876062 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 10214 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818702.pdf [firstpage_image] =>[orig_patent_app_number] => 11876062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876062
Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates Oct 21, 2007 Issued
Array ( [id] => 5582814 [patent_doc_number] => 20090102016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/876402 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4460 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20090102016.pdf [firstpage_image] =>[orig_patent_app_number] => 11876402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876402
DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES Oct 21, 2007 Abandoned
Array ( [id] => 5587522 [patent_doc_number] => 20090106724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design' [patent_app_type] => utility [patent_app_number] => 11/875032 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106724.pdf [firstpage_image] =>[orig_patent_app_number] => 11875032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/875032
Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design Oct 18, 2007 Issued
Array ( [id] => 7706531 [patent_doc_number] => 08091053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'System, method, and program for generating circuit' [patent_app_type] => utility [patent_app_number] => 11/907712 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091053.pdf [firstpage_image] =>[orig_patent_app_number] => 11907712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907712
System, method, and program for generating circuit Oct 15, 2007 Issued
Array ( [id] => 5286718 [patent_doc_number] => 20090100393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'METHOD AND APPARATUS FOR INCREMENTALLY COMPUTING CRITICALITY AND YIELD GRADIENT' [patent_app_type] => utility [patent_app_number] => 11/870672 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5198 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20090100393.pdf [firstpage_image] =>[orig_patent_app_number] => 11870672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/870672
Method and apparatus for incrementally computing criticality and yield gradient Oct 10, 2007 Issued
Array ( [id] => 5442929 [patent_doc_number] => 20090094568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Validation Of An Integrated Circuit For Electro Static Discharge Compliance' [patent_app_type] => utility [patent_app_number] => 11/867012 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094568.pdf [firstpage_image] =>[orig_patent_app_number] => 11867012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867012
Validation of an integrated circuit for electro static discharge compliance Oct 3, 2007 Issued
Array ( [id] => 5430416 [patent_doc_number] => 20090089726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Layout Quality Gauge for Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 11/865252 [patent_app_country] => US [patent_app_date] => 2007-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089726.pdf [firstpage_image] =>[orig_patent_app_number] => 11865252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/865252
Layout quality gauge for integrated circuit design Sep 30, 2007 Issued
Array ( [id] => 4895462 [patent_doc_number] => 20080104562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'METHOD AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/865242 [patent_app_country] => US [patent_app_date] => 2007-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5032 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104562.pdf [firstpage_image] =>[orig_patent_app_number] => 11865242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/865242
Method and program for designing semiconductor integrated circuit Sep 30, 2007 Issued
Array ( [id] => 5430419 [patent_doc_number] => 20090089729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Distorted Waveform Propagation and Crosstalk Delay Analysis Using Multiple Cell Models' [patent_app_type] => utility [patent_app_number] => 11/863252 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4564 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089729.pdf [firstpage_image] =>[orig_patent_app_number] => 11863252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863252
Distorted waveform propagation and crosstalk delay analysis using multiple cell models Sep 27, 2007 Issued
Array ( [id] => 5430415 [patent_doc_number] => 20090089725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'SYNTHESIS OF ASSERTIONS FROM STATEMENTS OF POWER INTENT' [patent_app_type] => utility [patent_app_number] => 11/863512 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089725.pdf [firstpage_image] =>[orig_patent_app_number] => 11863512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863512
Synthesis of assertions from statements of power intent Sep 27, 2007 Issued
Array ( [id] => 4755062 [patent_doc_number] => 20080163138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'POWER SUPPLY NOISE ANALYSIS MODEL GENERATING METHOD AND POWER SUPPLY NOISE ANALYSIS MODEL GENERATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/864122 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6665 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20080163138.pdf [firstpage_image] =>[orig_patent_app_number] => 11864122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864122
Power supply noise analysis model generating method and power supply noise analysis model generating apparatus Sep 27, 2007 Issued
Array ( [id] => 5510476 [patent_doc_number] => 20090083683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Method and Apparatus for Implementing Communication Between a Software Side and a Hardware Side of a Test Bench in a Transaction-Based Acceleration Verification System' [patent_app_type] => utility [patent_app_number] => 11/861952 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083683.pdf [firstpage_image] =>[orig_patent_app_number] => 11861952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861952
Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system Sep 25, 2007 Issued
Array ( [id] => 5508630 [patent_doc_number] => 20090081837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER' [patent_app_type] => utility [patent_app_number] => 11/861492 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5959 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20090081837.pdf [firstpage_image] =>[orig_patent_app_number] => 11861492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861492
Method for fabricating a semiconductor device having an extended stress liner Sep 25, 2007 Issued
Array ( [id] => 4722866 [patent_doc_number] => 20080244481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE AND SOFTWARE THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/859162 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244481.pdf [firstpage_image] =>[orig_patent_app_number] => 11859162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/859162
METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE AND SOFTWARE THEREFOR Sep 20, 2007 Abandoned
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