Leigh M. Garbowski

Array ( [id] => 180149 [patent_doc_number] => 07657865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Computer-readable recording medium recording a mask data generation program, mask data generation method, mask fabrication method, exposure method, and device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/855722 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11217 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657865.pdf [firstpage_image] =>[orig_patent_app_number] => 11855722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4923878 [patent_doc_number] => 20080072195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Validation processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/900822 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5496 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072195.pdf [firstpage_image] =>[orig_patent_app_number] => 11900822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5454694 [patent_doc_number] => 20090070731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Distributed Mask Data Preparation' [patent_app_type] => utility [patent_app_number] => 11/851342 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070731.pdf [firstpage_image] =>[orig_patent_app_number] => 11851342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7543002 [patent_doc_number] => 08060851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Method for operating a secure semiconductor IP server to support failure analysis' [patent_app_type] => utility [patent_app_number] => 11/850342 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5461 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060851.pdf [firstpage_image] =>[orig_patent_app_number] => 11850342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4774271 [patent_doc_number] => 20080059933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/845892 [patent_app_country] => US [patent_app_date] => 2007-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5003 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059933.pdf [firstpage_image] =>[orig_patent_app_number] => 11845892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5167283 [patent_doc_number] => 20070288872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'METHOD AND APPARATUS FOR CHARACTERISTIC IMPEDANCE DISCONTINUITY REDUCTION IN HIGH-SPEED FLEXIBLE CIRCUIT APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/842533 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2696 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288872.pdf [firstpage_image] =>[orig_patent_app_number] => 11842533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 166952 [patent_doc_number] => 07673280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Optical proximity correction (OPC) processing method for preventing the occurrence of off-grid' [patent_app_type] => utility [patent_app_number] => 11/841063 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673280.pdf [firstpage_image] =>[orig_patent_app_number] => 11841063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7591321 [patent_doc_number] => 07653886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Crosslinking of netlists' [patent_app_type] => utility [patent_app_number] => 11/840122 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/653/07653886.pdf [firstpage_image] =>[orig_patent_app_number] => 11840122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4747497 [patent_doc_number] => 20080092099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'ANALOG AND MIXED SIGNAL IC LAYOUT SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/839042 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8430 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092099.pdf [firstpage_image] =>[orig_patent_app_number] => 11839042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5444615 [patent_doc_number] => 20090045841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Method for Radiation Tolerance by Implant Well Notching' [patent_app_type] => utility [patent_app_number] => 11/838286 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045841.pdf [firstpage_image] =>[orig_patent_app_number] => 11838286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5444614 [patent_doc_number] => 20090045840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Method for Radiation Tolerance by Logic Book Folding' [patent_app_type] => utility [patent_app_number] => 11/838273 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045840.pdf [firstpage_image] =>[orig_patent_app_number] => 11838273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 137363 [patent_doc_number] => 07698682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Writing error verification method of pattern writing apparatus and generation apparatus of writing error verification data for pattern writing apparatus' [patent_app_type] => utility [patent_app_number] => 11/838542 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7808 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698682.pdf [firstpage_image] =>[orig_patent_app_number] => 11838542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 136722 [patent_doc_number] => 07703069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-20 [patent_title] => 'Three-dimensional mask model for photolithography simulation' [patent_app_type] => utility [patent_app_number] => 11/838582 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7197 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/703/07703069.pdf [firstpage_image] =>[orig_patent_app_number] => 11838582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 97622 [patent_doc_number] => 07739644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization' [patent_app_type] => utility [patent_app_number] => 11/838193 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5565 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739644.pdf [firstpage_image] =>[orig_patent_app_number] => 11838193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5086845 [patent_doc_number] => 20070276896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX' [patent_app_type] => utility [patent_app_number] => 11/836842 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20070276896.pdf [firstpage_image] =>[orig_patent_app_number] => 11836842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5363072 [patent_doc_number] => 20090037866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'ALTERNATING PHASE SHIFT MASK OPTIMIZATION FOR IMPROVED PROCESS WINDOW' [patent_app_type] => utility [patent_app_number] => 11/833462 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037866.pdf [firstpage_image] =>[orig_patent_app_number] => 11833462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4455162 [patent_doc_number] => 07966593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-21 [patent_title] => 'Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals' [patent_app_type] => utility [patent_app_number] => 11/832443 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5642 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966593.pdf [firstpage_image] =>[orig_patent_app_number] => 11832443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5363059 [patent_doc_number] => 20090037853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'ASYNCHRONOUS, MULTI-RAIL DIGITAL CIRCUIT WITH GATING AND GATED SUB-CIRCUITS AND METHOD FOR DESIGNING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/831942 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037853.pdf [firstpage_image] =>[orig_patent_app_number] => 11831942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 241486 [patent_doc_number] => 07594212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Automatic pin placement for integrated circuits to aid circuit board design' [patent_app_type] => utility [patent_app_number] => 11/888162 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594212.pdf [firstpage_image] =>[orig_patent_app_number] => 11888162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5363064 [patent_doc_number] => 20090037858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method For Automatic Maximization of Coverage in Constrained Stimulus Driven Simulation' [patent_app_type] => utility [patent_app_number] => 11/831673 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037858.pdf [firstpage_image] =>[orig_patent_app_number] => 11831673 [rel_patent_id] =>[rel_patent_doc_number] =>)