Leigh M. Garbowski

Array ( [id] => 147002 [patent_doc_number] => 07694253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Automatically generating an input sequence for a circuit design using mutant-based verification' [patent_app_type] => utility [patent_app_number] => 11/805902 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 43 [patent_no_of_words] => 23909 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694253.pdf [firstpage_image] =>[orig_patent_app_number] => 11805902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6376167 [patent_doc_number] => 20100301487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY' [patent_app_type] => utility [patent_app_number] => 12/599152 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3140 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301487.pdf [firstpage_image] =>[orig_patent_app_number] => 12599152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 47985 [patent_doc_number] => 07784014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Generation of a specification of a network packet processor' [patent_app_type] => utility [patent_app_number] => 11/799897 [patent_app_country] => US [patent_app_date] => 2007-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784014.pdf [firstpage_image] =>[orig_patent_app_number] => 11799897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4862647 [patent_doc_number] => 20080270960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHOD FOR INCORPORATING MILLER CAPACITANCE EFFECTS IN DIGITAL CIRCUITS FOR AN ACCURATE TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 11/741042 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270960.pdf [firstpage_image] =>[orig_patent_app_number] => 11741042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7595661 [patent_doc_number] => 07620921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'IC chip at-functional-speed testing with process coverage evaluation' [patent_app_type] => utility [patent_app_number] => 11/741164 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5811 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620921.pdf [firstpage_image] =>[orig_patent_app_number] => 11741164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5226771 [patent_doc_number] => 20070256038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 11/740184 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5935 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256038.pdf [firstpage_image] =>[orig_patent_app_number] => 11740184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 261951 [patent_doc_number] => 07574685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-11 [patent_title] => 'Method, system, and article of manufacture for reducing via failures in an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/739622 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4791 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574685.pdf [firstpage_image] =>[orig_patent_app_number] => 11739622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4889169 [patent_doc_number] => 20080263501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'System, Method, and Computer-Readable Medium for Performing Data Preparation for a Mask Design' [patent_app_type] => utility [patent_app_number] => 11/738844 [patent_app_country] => US [patent_app_date] => 2007-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263501.pdf [firstpage_image] =>[orig_patent_app_number] => 11738844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4889150 [patent_doc_number] => 20080263482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Method and Apparatus for Small Die Low Power System-on-Chip Design with Intelligent Power Supply Chip' [patent_app_type] => utility [patent_app_number] => 11/738222 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3039 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263482.pdf [firstpage_image] =>[orig_patent_app_number] => 11738222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 333424 [patent_doc_number] => 07512922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-31 [patent_title] => 'Methods of structured placement of a circuit design' [patent_app_type] => utility [patent_app_number] => 11/787812 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512922.pdf [firstpage_image] =>[orig_patent_app_number] => 11787812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722842 [patent_doc_number] => 20080244474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Cell library management for power optimization' [patent_app_type] => utility [patent_app_number] => 11/732092 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244474.pdf [firstpage_image] =>[orig_patent_app_number] => 11732092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7689764 [patent_doc_number] => 20070234269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Light intensity distribution simulation method and computer program product' [patent_app_type] => utility [patent_app_number] => 11/730102 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12326 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234269.pdf [firstpage_image] =>[orig_patent_app_number] => 11730102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722896 [patent_doc_number] => 20080244490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Sequence-pair creating apparatus and sequence-pair creating method' [patent_app_type] => utility [patent_app_number] => 11/730004 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 29968 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244490.pdf [firstpage_image] =>[orig_patent_app_number] => 11730004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7593621 [patent_doc_number] => 07627846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Method and apparatus for automatically shaping traces on surface of substrate of semiconductor package by using computation' [patent_app_type] => utility [patent_app_number] => 11/723724 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 8354 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/627/07627846.pdf [firstpage_image] =>[orig_patent_app_number] => 11723724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 245224 [patent_doc_number] => 07590968 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Methods for risk-informed chip layout generation' [patent_app_type] => utility [patent_app_number] => 11/680552 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9023 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590968.pdf [firstpage_image] =>[orig_patent_app_number] => 11680552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 261948 [patent_doc_number] => 07574682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Yield analysis and improvement using electrical sensitivity extraction' [patent_app_type] => utility [patent_app_number] => 11/680012 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10946 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574682.pdf [firstpage_image] =>[orig_patent_app_number] => 11680012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730424 [patent_doc_number] => 20080209160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Device, System and Method of Verification of Address Translation Mechanisms' [patent_app_type] => utility [patent_app_number] => 11/679192 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209160.pdf [firstpage_image] =>[orig_patent_app_number] => 11679192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4723977 [patent_doc_number] => 20080203518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES' [patent_app_type] => utility [patent_app_number] => 11/678922 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5425 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203518.pdf [firstpage_image] =>[orig_patent_app_number] => 11678922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 128312 [patent_doc_number] => 07707528 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-27 [patent_title] => 'System and method for performing verification based upon both rules and models' [patent_app_type] => utility [patent_app_number] => 11/678592 [patent_app_country] => US [patent_app_date] => 2007-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3607 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707528.pdf [firstpage_image] =>[orig_patent_app_number] => 11678592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5226772 [patent_doc_number] => 20070256039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'DUMMY FILL FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/678542 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 17812 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256039.pdf [firstpage_image] =>[orig_patent_app_number] => 11678542 [rel_patent_id] =>[rel_patent_doc_number] =>)