Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 347186 [patent_doc_number] => 07500216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-03 [patent_title] => 'Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines' [patent_app_type] => utility [patent_app_number] => 11/703372 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12170 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/500/07500216.pdf [firstpage_image] =>[orig_patent_app_number] => 11703372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703372
Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines Feb 6, 2007 Issued
Array ( [id] => 5047684 [patent_doc_number] => 20070266358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Yield calculation method' [patent_app_type] => utility [patent_app_number] => 11/702642 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6476 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20070266358.pdf [firstpage_image] =>[orig_patent_app_number] => 11702642 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702642
Yield calculation method Feb 5, 2007 Abandoned
Array ( [id] => 235201 [patent_doc_number] => 07600208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'Automatic placement of decoupling capacitors' [patent_app_type] => utility [patent_app_number] => 11/669872 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 9431 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600208.pdf [firstpage_image] =>[orig_patent_app_number] => 11669872 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669872
Automatic placement of decoupling capacitors Jan 30, 2007 Issued
Array ( [id] => 4747487 [patent_doc_number] => 20080092089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'CAD data processing apparatus, CAD data processing method, and computer product' [patent_app_type] => utility [patent_app_number] => 11/700144 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11177 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092089.pdf [firstpage_image] =>[orig_patent_app_number] => 11700144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700144
CAD data processing apparatus, CAD data processing method, and computer product Jan 30, 2007 Abandoned
Array ( [id] => 4847780 [patent_doc_number] => 20080184188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Integrated Circuit Design Method for Efficiently Generating Mask Data' [patent_app_type] => utility [patent_app_number] => 11/669202 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6301 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184188.pdf [firstpage_image] =>[orig_patent_app_number] => 11669202 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669202
Integrated circuit design method for efficiently generating mask data Jan 30, 2007 Issued
Array ( [id] => 97611 [patent_doc_number] => 07739641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'Integrated circuit having a clock tree' [patent_app_type] => utility [patent_app_number] => 11/700532 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739641.pdf [firstpage_image] =>[orig_patent_app_number] => 11700532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700532
Integrated circuit having a clock tree Jan 30, 2007 Issued
Array ( [id] => 5069709 [patent_doc_number] => 20070190811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Method of forming patterns and/or pattern data for controlling pattern density of semiconductor devices and pattern density controlled semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/655222 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190811.pdf [firstpage_image] =>[orig_patent_app_number] => 11655222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655222
Method of forming patterns and/or pattern data for controlling pattern density of semiconductor devices and pattern density controlled semiconductor devices Jan 18, 2007 Abandoned
Array ( [id] => 294267 [patent_doc_number] => 07546567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 11/652302 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5700 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546567.pdf [firstpage_image] =>[orig_patent_app_number] => 11652302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652302
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip Jan 9, 2007 Issued
Array ( [id] => 5115047 [patent_doc_number] => 20070198963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'CALCULATION SYSTEM FOR INVERSE MASKS' [patent_app_type] => utility [patent_app_number] => 11/621082 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 19580 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198963.pdf [firstpage_image] =>[orig_patent_app_number] => 11621082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621082
Calculation system for inverse masks Jan 7, 2007 Issued
Array ( [id] => 172005 [patent_doc_number] => 07669173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Semiconductor mask and method of making same' [patent_app_type] => utility [patent_app_number] => 11/635322 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3275 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669173.pdf [firstpage_image] =>[orig_patent_app_number] => 11635322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635322
Semiconductor mask and method of making same Dec 6, 2006 Issued
Array ( [id] => 4783116 [patent_doc_number] => 20080136445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Synchronous elastic designs with early evaluation' [patent_app_type] => utility [patent_app_number] => 11/634462 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10135 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136445.pdf [firstpage_image] =>[orig_patent_app_number] => 11634462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/634462
Synchronous elastic designs with early evaluation Dec 5, 2006 Issued
Array ( [id] => 19180 [patent_doc_number] => 07810055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Design independent correlation data storage for use with physical design of programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/633962 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7272 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/810/07810055.pdf [firstpage_image] =>[orig_patent_app_number] => 11633962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/633962
Design independent correlation data storage for use with physical design of programmable logic devices Dec 4, 2006 Issued
Array ( [id] => 5064930 [patent_doc_number] => 20070226572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Soft error rate analysis system' [patent_app_type] => utility [patent_app_number] => 11/592712 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10606 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226572.pdf [firstpage_image] =>[orig_patent_app_number] => 11592712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/592712
Soft error rate analysis system Nov 1, 2006 Abandoned
Array ( [id] => 5156084 [patent_doc_number] => 20070038967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'System and method for design, procurement and manufacturing collaboration' [patent_app_type] => utility [patent_app_number] => 11/585370 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7263 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20070038967.pdf [firstpage_image] =>[orig_patent_app_number] => 11585370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585370
System and method for design, procurement and manufacturing collaboration Oct 23, 2006 Issued
Array ( [id] => 4969701 [patent_doc_number] => 20070109703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS, ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/548012 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10927 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109703.pdf [firstpage_image] =>[orig_patent_app_number] => 11548012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548012
SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS, ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS Oct 9, 2006 Abandoned
Array ( [id] => 158073 [patent_doc_number] => 07685557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Radiation mask with spatially variable transmissivity' [patent_app_type] => utility [patent_app_number] => 11/538912 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 12313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685557.pdf [firstpage_image] =>[orig_patent_app_number] => 11538912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538912
Radiation mask with spatially variable transmissivity Oct 4, 2006 Issued
Array ( [id] => 5195359 [patent_doc_number] => 20070083844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Logic circuit design support apparatus, and logic circuit design support method employing this apparatus' [patent_app_type] => utility [patent_app_number] => 11/542272 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083844.pdf [firstpage_image] =>[orig_patent_app_number] => 11542272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542272
Logic circuit design support apparatus, and logic circuit design support method employing this apparatus Oct 3, 2006 Abandoned
Array ( [id] => 4934930 [patent_doc_number] => 20080005705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Description style conversion method, program, and system of logic circuit' [patent_app_type] => utility [patent_app_number] => 11/540654 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 86 [patent_figures_cnt] => 86 [patent_no_of_words] => 15190 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005705.pdf [firstpage_image] =>[orig_patent_app_number] => 11540654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540654
Description style conversion method, program, and system of logic circuit Oct 1, 2006 Issued
Array ( [id] => 235228 [patent_doc_number] => 07600212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Method of compensating photomask data for the effects of etch and lithography processes' [patent_app_type] => utility [patent_app_number] => 11/541921 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7013 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600212.pdf [firstpage_image] =>[orig_patent_app_number] => 11541921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/541921
Method of compensating photomask data for the effects of etch and lithography processes Oct 1, 2006 Issued
Array ( [id] => 591100 [patent_doc_number] => 07464355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Timing analyzing method and apparatus for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/540645 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4528 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464355.pdf [firstpage_image] =>[orig_patent_app_number] => 11540645 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540645
Timing analyzing method and apparatus for semiconductor integrated circuit Oct 1, 2006 Issued
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