Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20304415 [patent_doc_number] => 12450408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Machine learning for selecting initial source shapes for source mask optimization [patent_app_type] => utility [patent_app_number] => 17/829714 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 1144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829714
Machine learning for selecting initial source shapes for source mask optimization May 31, 2022 Issued
Array ( [id] => 18607083 [patent_doc_number] => 11748551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Optical mode optimization for wafer inspection [patent_app_type] => utility [patent_app_number] => 17/827529 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827529
Optical mode optimization for wafer inspection May 26, 2022 Issued
Array ( [id] => 18966267 [patent_doc_number] => 11900037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Circuit synthesis optimization for implements on integrated circuit [patent_app_type] => utility [patent_app_number] => 17/752333 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752333
Circuit synthesis optimization for implements on integrated circuit May 23, 2022 Issued
Array ( [id] => 18038726 [patent_doc_number] => 20220382942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => NON-FUNCTIONAL LOOPBACK-PATHS REMOVAL FROM IO-PADS USING LOGIC REPLICATION [patent_app_type] => utility [patent_app_number] => 17/750777 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750777
Non-functional loopback-paths removal from IO-pads using logic replication May 22, 2022 Issued
Array ( [id] => 20266141 [patent_doc_number] => 12437134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Deterministic netlist transformations in a multi-processor parallel computing system [patent_app_type] => utility [patent_app_number] => 17/751253 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751253
Deterministic netlist transformations in a multi-processor parallel computing system May 22, 2022 Issued
Array ( [id] => 20610249 [patent_doc_number] => 12585851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Systems and methods for tracking synthesis optimizations for circuit designs [patent_app_type] => utility [patent_app_number] => 17/746924 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746924
Systems and methods for tracking synthesis optimizations for circuit designs May 16, 2022 Issued
Array ( [id] => 19933981 [patent_doc_number] => 12307186 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Launch off shift process [patent_app_type] => utility [patent_app_number] => 17/737221 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737221
Launch off shift process May 4, 2022 Issued
Array ( [id] => 18493598 [patent_doc_number] => 11699016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Passively cooling hardware components [patent_app_type] => utility [patent_app_number] => 17/726352 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6058 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726352
Passively cooling hardware components Apr 20, 2022 Issued
Array ( [id] => 17778969 [patent_doc_number] => 20220245319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => METHOD FOR INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/719336 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719336
Method for integrated circuit design Apr 11, 2022 Issued
Array ( [id] => 20131313 [patent_doc_number] => 12373626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Method and non-transitory computer readable medium [patent_app_type] => utility [patent_app_number] => 17/719332 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 1047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719332
Method and non-transitory computer readable medium Apr 11, 2022 Issued
Array ( [id] => 18695146 [patent_doc_number] => 20230325566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => AUTOMATIC CONFIGURATION OF PIPELINE MODULES IN AN ELECTRONICS SYSTEM [patent_app_type] => utility [patent_app_number] => 17/717133 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717133
Automatic configuration of pipeline modules in an electronics system Apr 10, 2022 Issued
Array ( [id] => 18430740 [patent_doc_number] => 11675962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Vertex-based OPC for opening patterning [patent_app_type] => utility [patent_app_number] => 17/712974 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 12254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712974
Vertex-based OPC for opening patterning Apr 3, 2022 Issued
Array ( [id] => 18678318 [patent_doc_number] => 20230315966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => FEED-FORWARD DESIGN OF THREE-DIMENSIONAL QUANTUM CHIPS [patent_app_type] => utility [patent_app_number] => 17/657543 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657543
Feed-forward design of three-dimensional quantum chips Mar 30, 2022 Issued
Array ( [id] => 19885952 [patent_doc_number] => 12271669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Executing instruction sequences generated from software interactions as part of formal verification of a design under test [patent_app_type] => utility [patent_app_number] => 17/709192 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709192
Executing instruction sequences generated from software interactions as part of formal verification of a design under test Mar 29, 2022 Issued
Array ( [id] => 17916073 [patent_doc_number] => 20220318469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => Systems, Methods, and Devices for Virtual Prototyping [patent_app_type] => utility [patent_app_number] => 17/707734 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707734
Systems, Methods, and Devices for Virtual Prototyping Mar 28, 2022 Pending
Array ( [id] => 18966273 [patent_doc_number] => 11900043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Electronic device for manufacturing semiconductor device and operating method of electronic device [patent_app_type] => utility [patent_app_number] => 17/701520 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701520
Electronic device for manufacturing semiconductor device and operating method of electronic device Mar 21, 2022 Issued
Array ( [id] => 17885210 [patent_doc_number] => 20220300687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => Propagating Physical Design Information Through Logical Design Hierarchy of an Electronic Circuit [patent_app_type] => utility [patent_app_number] => 17/695712 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695712
Propagating physical design information through logical design hierarchy of an electronic circuit Mar 14, 2022 Issued
Array ( [id] => 18630613 [patent_doc_number] => 20230289507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => ANALYZING INTEGRATED CIRCUIT TIMING VARIATION [patent_app_type] => utility [patent_app_number] => 17/693122 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693122
ANALYZING INTEGRATED CIRCUIT TIMING VARIATION Mar 10, 2022 Pending
Array ( [id] => 17690829 [patent_doc_number] => 20220198122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING SAME AND A SYSTEM [patent_app_type] => utility [patent_app_number] => 17/692767 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692767
Integrated circuit and method of forming same and a system Mar 10, 2022 Issued
Array ( [id] => 20079742 [patent_doc_number] => 12353811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Out-of-context timing constraints modification for interior pins [patent_app_type] => utility [patent_app_number] => 17/674890 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674890
Out-of-context timing constraints modification for interior pins Feb 17, 2022 Issued
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