Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18407900 [patent_doc_number] => 20230169253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => USE OF ADAPTIVE REPLACEMENT MAPS IN DIGITAL LITHOGRAPHY FOR LOCAL CELL REPLACEMENT [patent_app_type] => utility [patent_app_number] => 17/457195 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457195
Use of adaptive replacement maps in digital lithography for local cell replacement Nov 30, 2021 Issued
Array ( [id] => 18819875 [patent_doc_number] => 20230394215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CHIP AND PINOUT DESIGN METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/270215 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 632 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18270215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/270215
Chip and pinout design method therefor Nov 29, 2021 Issued
Array ( [id] => 19427101 [patent_doc_number] => 12086523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries [patent_app_type] => utility [patent_app_number] => 17/456847 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 7872 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456847
Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries Nov 28, 2021 Issued
Array ( [id] => 18856085 [patent_doc_number] => 11853669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Relocatable FPGA modules [patent_app_type] => utility [patent_app_number] => 17/532599 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532599
Relocatable FPGA modules Nov 21, 2021 Issued
Array ( [id] => 19413110 [patent_doc_number] => 12078924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Layout correction method [patent_app_type] => utility [patent_app_number] => 17/530564 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2627 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530564
Layout correction method Nov 18, 2021 Issued
Array ( [id] => 18446279 [patent_doc_number] => 11681851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Hierarchical density uniformization for semiconductor feature surface planarization [patent_app_type] => utility [patent_app_number] => 17/531507 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531507
Hierarchical density uniformization for semiconductor feature surface planarization Nov 18, 2021 Issued
Array ( [id] => 18990016 [patent_doc_number] => 20240061985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => ANALOGUE CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/267247 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18267247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/267247
ANALOGUE CIRCUIT DESIGN Nov 15, 2021 Pending
Array ( [id] => 18359285 [patent_doc_number] => 20230140876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => THREE-DIMENSIONAL FPGA WITH STRUCTURE ASIC HARDENING CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/523525 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523525
Three-dimensional FPGA with structure ASIC hardening capability Nov 9, 2021 Issued
Array ( [id] => 17597371 [patent_doc_number] => 20220146945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => STOCHASTIC-AWARE LITHOGRAPHIC MODELS FOR MASK SYNTHESIS [patent_app_type] => utility [patent_app_number] => 17/522574 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522574
Stochastic-aware lithographic models for mask synthesis Nov 8, 2021 Issued
Array ( [id] => 18370951 [patent_doc_number] => 11651129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Selecting a subset of training data from a data pool for a power prediction model [patent_app_type] => utility [patent_app_number] => 17/520437 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7708 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520437
Selecting a subset of training data from a data pool for a power prediction model Nov 4, 2021 Issued
Array ( [id] => 17581641 [patent_doc_number] => 20220138496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => POWER ESTIMATION USING INPUT VECTORS AND DEEP RECURRENT NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 17/520438 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520438
Power estimation using input vectors and deep recurrent neural networks Nov 4, 2021 Issued
Array ( [id] => 18316853 [patent_doc_number] => 11630935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-18 [patent_title] => Data traffic injection for simulation of circuit designs [patent_app_type] => utility [patent_app_number] => 17/498048 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498048
Data traffic injection for simulation of circuit designs Oct 10, 2021 Issued
Array ( [id] => 18330998 [patent_doc_number] => 11636244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-25 [patent_title] => Performance tuning of a hardware description language simulator [patent_app_type] => utility [patent_app_number] => 17/490897 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10855 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490897 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490897
Performance tuning of a hardware description language simulator Sep 29, 2021 Issued
Array ( [id] => 18811181 [patent_doc_number] => 20230385517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => PRINTED CIRCUIT BOARD AND METHOD FOR DESIGNING THE SAME [patent_app_type] => utility [patent_app_number] => 18/245980 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245980
Printed circuit board and method for designing the same Sep 26, 2021 Issued
Array ( [id] => 18286547 [patent_doc_number] => 20230102019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD COMPONENT PLACEMENT AND APPROVAL [patent_app_type] => utility [patent_app_number] => 17/485634 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485634
Methods and systems for printed circuit board component placement and approval Sep 26, 2021 Issued
Array ( [id] => 17940743 [patent_doc_number] => 11475199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Parallelizing simulation and hardware co-simulation of circuit designs through partitioning [patent_app_type] => utility [patent_app_number] => 17/486547 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486547
Parallelizing simulation and hardware co-simulation of circuit designs through partitioning Sep 26, 2021 Issued
Array ( [id] => 19212709 [patent_doc_number] => 12001772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Ultra-short-height standard cell architecture [patent_app_type] => utility [patent_app_number] => 17/485088 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485088
Ultra-short-height standard cell architecture Sep 23, 2021 Issued
Array ( [id] => 17484741 [patent_doc_number] => 20220092245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => ENDPOINT PATH MARGIN BASED INTEGRATED CIRCUIT DESIGN USING SUB-CRITICAL TIMING PATHS [patent_app_type] => utility [patent_app_number] => 17/478882 [patent_app_country] => US [patent_app_date] => 2021-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478882
Endpoint path margin based integrated circuit design using sub-critical timing paths Sep 17, 2021 Issued
Array ( [id] => 19355983 [patent_doc_number] => 12056431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Methods of preparing photo mask data and manufacturing a photo mask [patent_app_type] => utility [patent_app_number] => 17/462832 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462832
Methods of preparing photo mask data and manufacturing a photo mask Aug 30, 2021 Issued
Array ( [id] => 18506653 [patent_doc_number] => 11704471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Three-dimensional mask simulations based on feature images [patent_app_type] => utility [patent_app_number] => 17/463075 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6017 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463075
Three-dimensional mask simulations based on feature images Aug 30, 2021 Issued
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