Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17276848 [patent_doc_number] => 20210383046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => Systems and Methods for Multi-Bit Memory With Embedded Logic [patent_app_type] => utility [patent_app_number] => 17/409894 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409894
Systems and methods for multi-bit memory with embedded logic Aug 23, 2021 Issued
Array ( [id] => 17401861 [patent_doc_number] => 20220043951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 17/409566 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409566
Generating integrated circuit floorplans using neural networks Aug 22, 2021 Issued
Array ( [id] => 18660285 [patent_doc_number] => 20230306293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => QUANTUM CIRCUIT GENERATION DEVICE, QUANTUM CIRCUIT GENERATION METHOD, AND QUANTUM CIRCUIT GENERATION PROGRAM [patent_app_type] => utility [patent_app_number] => 18/022097 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18022097 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/022097
QUANTUM CIRCUIT GENERATION DEVICE, QUANTUM CIRCUIT GENERATION METHOD, AND QUANTUM CIRCUIT GENERATION PROGRAM Aug 17, 2021 Abandoned
Array ( [id] => 19398795 [patent_doc_number] => 12073163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Cell regions of integrated circuits and methods of making same [patent_app_type] => utility [patent_app_number] => 17/405626 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405626
Cell regions of integrated circuits and methods of making same Aug 17, 2021 Issued
Array ( [id] => 18547379 [patent_doc_number] => 11720732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications [patent_app_type] => utility [patent_app_number] => 17/402739 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402739
Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications Aug 15, 2021 Issued
Array ( [id] => 18193374 [patent_doc_number] => 20230046893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => METHODS AND SYSTEMS FOR LEVERAGING COMPUTER-AIDED DESIGN VARIABILITY IN SYNTHESIS TUNING [patent_app_type] => utility [patent_app_number] => 17/444860 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17444860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/444860
Methods and systems for leveraging computer-aided design variability in synthesis tuning Aug 10, 2021 Issued
Array ( [id] => 18386421 [patent_doc_number] => 11657204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Method of wafer layout and exposure system of lithography machine [patent_app_type] => utility [patent_app_number] => 17/395637 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4931 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395637
Method of wafer layout and exposure system of lithography machine Aug 5, 2021 Issued
Array ( [id] => 17402052 [patent_doc_number] => 20220044142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => QUANTUM COMPUTING UNIT WITH MAJORANA MODES [patent_app_type] => utility [patent_app_number] => 17/396151 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396151
Quantum computing unit with majorana modes Aug 5, 2021 Issued
Array ( [id] => 18527952 [patent_doc_number] => 11714946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Standard cell and semiconductor device including anchor nodes and method of making [patent_app_type] => utility [patent_app_number] => 17/395193 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395193
Standard cell and semiconductor device including anchor nodes and method of making Aug 4, 2021 Issued
Array ( [id] => 18179897 [patent_doc_number] => 20230040626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => THERMAL TRANSFER SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/393885 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393885
Thermal transfer system and method Aug 3, 2021 Issued
Array ( [id] => 18184747 [patent_doc_number] => 20230045477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => FLEXIBLE RECHARGER WITH INTEGRATED ELECTRONICS [patent_app_type] => utility [patent_app_number] => 17/394348 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/394348
Flexible recharger with integrated electronics Aug 3, 2021 Issued
Array ( [id] => 19294425 [patent_doc_number] => 12033787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Thermal transfer system and method [patent_app_type] => utility [patent_app_number] => 17/393965 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6151 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393965
Thermal transfer system and method Aug 3, 2021 Issued
Array ( [id] => 19062101 [patent_doc_number] => 11941337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => System and method for modeling nonlinear component for use in circuit design [patent_app_type] => utility [patent_app_number] => 17/390882 [patent_app_country] => US [patent_app_date] => 2021-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390882
System and method for modeling nonlinear component for use in circuit design Jul 30, 2021 Issued
Array ( [id] => 18430736 [patent_doc_number] => 11675958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Lithography simulation method [patent_app_type] => utility [patent_app_number] => 17/390833 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390833
Lithography simulation method Jul 29, 2021 Issued
Array ( [id] => 18687371 [patent_doc_number] => 11783110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method for reticle enhancement technology of a design pattern to be manufactured on a substrate [patent_app_type] => utility [patent_app_number] => 17/444140 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 10206 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17444140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/444140
Method for reticle enhancement technology of a design pattern to be manufactured on a substrate Jul 29, 2021 Issued
Array ( [id] => 17232969 [patent_doc_number] => 20210359526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SERIES-CONNECTED BATTERY PACKS, SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/389770 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389770
Series-connected battery packs, system and method Jul 29, 2021 Issued
Array ( [id] => 18527957 [patent_doc_number] => 11714951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Geometric mask rule check with favorable and unfavorable zones [patent_app_type] => utility [patent_app_number] => 17/386737 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386737
Geometric mask rule check with favorable and unfavorable zones Jul 27, 2021 Issued
Array ( [id] => 18370957 [patent_doc_number] => 11651135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Dose optimization techniques for mask synthesis tools [patent_app_type] => utility [patent_app_number] => 17/384465 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384465 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384465
Dose optimization techniques for mask synthesis tools Jul 22, 2021 Issued
Array ( [id] => 18386415 [patent_doc_number] => 11657198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Verification of hardware design for data transformation component [patent_app_type] => utility [patent_app_number] => 17/384599 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384599
Verification of hardware design for data transformation component Jul 22, 2021 Issued
Array ( [id] => 17374214 [patent_doc_number] => 20220029266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => QUANTUM CHIP PREPARATION METHOD, APPARATUS, AND DEVICE AND QUANTUM CHIP [patent_app_type] => utility [patent_app_number] => 17/381758 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381758
QUANTUM CHIP PREPARATION METHOD, APPARATUS, AND DEVICE AND QUANTUM CHIP Jul 20, 2021 Abandoned
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