Search

Leo B Tentoni

Examiner (ID: 106, Phone: (571)272-1209 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1732, 1307, 1791
Total Applications
4174
Issued Applications
3256
Pending Applications
267
Abandoned Applications
650

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16272323 [patent_doc_number] => 20200273811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => IC DIE PACKAGE THERMAL SPREADER AND EMI SHIELD COMPRISING GRAPHITE [patent_app_type] => utility [patent_app_number] => 16/287665 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287665
IC DIE PACKAGE THERMAL SPREADER AND EMI SHIELD COMPRISING GRAPHITE Feb 26, 2019 Abandoned
Array ( [id] => 16356460 [patent_doc_number] => 10796978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => TIM strain mitigation in electronic modules [patent_app_type] => utility [patent_app_number] => 16/285378 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 3478 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16285378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/285378
TIM strain mitigation in electronic modules Feb 25, 2019 Issued
Array ( [id] => 16386521 [patent_doc_number] => 10811366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Microelectronic bond pads having integrated spring structures [patent_app_type] => utility [patent_app_number] => 16/249457 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4881 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249457 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249457
Microelectronic bond pads having integrated spring structures Jan 15, 2019 Issued
Array ( [id] => 14110327 [patent_doc_number] => 20190096839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => Substrate and Package Structure [patent_app_type] => utility [patent_app_number] => 16/199507 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/199507
Substrate and package structure Nov 25, 2018 Issued
Array ( [id] => 19168525 [patent_doc_number] => 11984439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Microelectronic assemblies [patent_app_type] => utility [patent_app_number] => 16/161578 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 16994 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16161578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/161578
Microelectronic assemblies Oct 15, 2018 Issued
Array ( [id] => 13936031 [patent_doc_number] => 20190051531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => CONTACT INTEGRATION AND SELECTIVE SILICIDE FORMATION METHODS [patent_app_type] => utility [patent_app_number] => 16/159608 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159608 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/159608
Contact integration and selective silicide formation methods Oct 11, 2018 Issued
Array ( [id] => 14079465 [patent_doc_number] => 20190088620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => NOVEL INTEGRATED CIRCUIT STACKING APPROACH [patent_app_type] => utility [patent_app_number] => 16/152561 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152561 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152561
Integrated circuit stacking approach Oct 4, 2018 Issued
Array ( [id] => 15688057 [patent_doc_number] => 20200098692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => MICROELECTRONIC ASSEMBLIES HAVING NON-RECTILINEAR ARRANGEMENTS [patent_app_type] => utility [patent_app_number] => 16/142233 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142233
MICROELECTRONIC ASSEMBLIES HAVING NON-RECTILINEAR ARRANGEMENTS Sep 25, 2018 Abandoned
Array ( [id] => 14079883 [patent_doc_number] => 20190088829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => LIGHT SOURCE AND ILLUMINATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/135241 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/135241
LIGHT SOURCE AND ILLUMINATION DEVICE Sep 18, 2018 Abandoned
Array ( [id] => 14110271 [patent_doc_number] => 20190096811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/135684 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/135684
Integrated circuit and method of manufacturing same Sep 18, 2018 Issued
Array ( [id] => 14079697 [patent_doc_number] => 20190088736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/135323 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/135323
Semiconductor device Sep 18, 2018 Issued
Array ( [id] => 15657627 [patent_doc_number] => 20200091344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => ASYMMETRIC THRESHOLD VOLTAGE FINFET DEVICE BY PARTIAL CHANNEL DOPING VARIATION [patent_app_type] => utility [patent_app_number] => 16/134543 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134543
Asymmetric threshold voltage FinFET device by partial channel doping variation Sep 17, 2018 Issued
Array ( [id] => 16201954 [patent_doc_number] => 10727133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Method of forming gate structure with undercut region and resulting device [patent_app_type] => utility [patent_app_number] => 16/134708 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2795 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134708 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134708
Method of forming gate structure with undercut region and resulting device Sep 17, 2018 Issued
Array ( [id] => 14985213 [patent_doc_number] => 10446527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Stacked semiconductor dies including inductors and associated methods [patent_app_type] => utility [patent_app_number] => 16/128414 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7744 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128414
Stacked semiconductor dies including inductors and associated methods Sep 10, 2018 Issued
Array ( [id] => 16653440 [patent_doc_number] => 10930633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Buffer design for package integration [patent_app_type] => utility [patent_app_number] => 16/120752 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/120752
Buffer design for package integration Sep 3, 2018 Issued
Array ( [id] => 15598063 [patent_doc_number] => 20200075566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => INTEGRATED CIRCUIT (IC) DEVICE WITH MULTI-DIE INTEGRATION [patent_app_type] => utility [patent_app_number] => 16/119137 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119137
Integrated circuit (IC) device with multi-die integration Aug 30, 2018 Issued
Array ( [id] => 16132507 [patent_doc_number] => 10700021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Coreless organic packages with embedded die and magnetic inductor structures [patent_app_type] => utility [patent_app_number] => 16/119923 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 7879 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119923
Coreless organic packages with embedded die and magnetic inductor structures Aug 30, 2018 Issued
Array ( [id] => 16386457 [patent_doc_number] => 10811302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same [patent_app_type] => utility [patent_app_number] => 16/117923 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4858 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117923
Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same Aug 29, 2018 Issued
Array ( [id] => 15597951 [patent_doc_number] => 20200075510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/116915 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116915
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Aug 29, 2018 Abandoned
Array ( [id] => 16410072 [patent_doc_number] => 10818636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Substrate panel structure and manufacturing process [patent_app_type] => utility [patent_app_number] => 16/118235 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 60 [patent_no_of_words] => 28866 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118235
Substrate panel structure and manufacturing process Aug 29, 2018 Issued
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