Search

Leo B Tentoni

Examiner (ID: 106, Phone: (571)272-1209 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1732, 1307, 1791
Total Applications
4174
Issued Applications
3256
Pending Applications
267
Abandoned Applications
650

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13976719 [patent_doc_number] => 10217726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Stacked semiconductor dies including inductors and associated methods [patent_app_type] => utility [patent_app_number] => 15/693039 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7716 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693039 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693039
Stacked semiconductor dies including inductors and associated methods Aug 30, 2017 Issued
Array ( [id] => 13995975 [patent_doc_number] => 20190067145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/683059 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683059 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683059
SEMICONDUCTOR DEVICE Aug 21, 2017 Abandoned
Array ( [id] => 15791493 [patent_doc_number] => 10629478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Dual-damascene formation with dielectric spacer and thin liner [patent_app_type] => utility [patent_app_number] => 15/682773 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682773 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682773
Dual-damascene formation with dielectric spacer and thin liner Aug 21, 2017 Issued
Array ( [id] => 13709251 [patent_doc_number] => 20170365580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/676350 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676350 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676350
Semiconductor package and fabrication method thereof Aug 13, 2017 Issued
Array ( [id] => 15889591 [patent_doc_number] => 10651151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => 3D integration using Al--Ge eutectic bond interconnect [patent_app_type] => utility [patent_app_number] => 15/663242 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4268 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/663242
3D integration using Al--Ge eutectic bond interconnect Jul 27, 2017 Issued
Array ( [id] => 15375923 [patent_doc_number] => 10529689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Semiconductor package with multiple coplanar interposers [patent_app_type] => utility [patent_app_number] => 15/660210 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 6132 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15660210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/660210
Semiconductor package with multiple coplanar interposers Jul 25, 2017 Issued
Array ( [id] => 14459777 [patent_doc_number] => 10325862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Wafer rigidity with reinforcement structure [patent_app_type] => utility [patent_app_number] => 15/657666 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 3665 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/657666
Wafer rigidity with reinforcement structure Jul 23, 2017 Issued
Array ( [id] => 12188858 [patent_doc_number] => 20180047794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'OLED TOUCH DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 15/656127 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2706 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/656127
OLED touch display panel Jul 20, 2017 Issued
Array ( [id] => 13723991 [patent_doc_number] => 20170372951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => METHOD AND PROCESSING APPARATUS FOR PERFORMING PRE-TREATMENT TO FORM COPPER WIRING IN RECESS FORMED IN SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/627478 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627478 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627478
Method and processing apparatus for performing pre-treatment to form copper wiring in recess formed in substrate Jun 19, 2017 Issued
Array ( [id] => 11983676 [patent_doc_number] => 20170287831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'LOCALIZED HIGH DENSITY SUBSTRATE ROUTING' [patent_app_type] => utility [patent_app_number] => 15/620555 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620555
Localized high density substrate routing Jun 11, 2017 Issued
Array ( [id] => 11967134 [patent_doc_number] => 20170271287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'Interconnect Structure and Method of Forming Same' [patent_app_type] => utility [patent_app_number] => 15/613579 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613579
Interconnect structure and method of forming same Jun 4, 2017 Issued
Array ( [id] => 11967070 [patent_doc_number] => 20170271223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'System and Method for Bonding Package Lid' [patent_app_type] => utility [patent_app_number] => 15/613815 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613815
System and method for bonding package lid Jun 4, 2017 Issued
Array ( [id] => 16214947 [patent_doc_number] => 10730745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor device and method of forming MEMS package [patent_app_type] => utility [patent_app_number] => 15/610997 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 66 [patent_no_of_words] => 20057 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/610997
Semiconductor device and method of forming MEMS package May 31, 2017 Issued
Array ( [id] => 16372427 [patent_doc_number] => 10804193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Semiconductor interconnect structure with double conductors [patent_app_type] => utility [patent_app_number] => 15/609672 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3449 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609672
Semiconductor interconnect structure with double conductors May 30, 2017 Issued
Array ( [id] => 11959377 [patent_doc_number] => 20170263529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'THICK-SILVER LAYER INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/608660 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608660 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608660
Thick-silver layer interface May 29, 2017 Issued
Array ( [id] => 13921893 [patent_doc_number] => 10205072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Light-emitting device and method of preparing same, optical semiconductor element mounting package, and optical semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 15/603618 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603618 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603618
Light-emitting device and method of preparing same, optical semiconductor element mounting package, and optical semiconductor device using the same May 23, 2017 Issued
Array ( [id] => 11952527 [patent_doc_number] => 20170256678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'LIGHT-EMITTING ELEMENT HAVING A REFLECTIVE STRUCTURE WITH HIGH EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 15/602421 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602421 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/602421
Light-emitting element having a reflective structure with high efficiency May 22, 2017 Issued
Array ( [id] => 15760653 [patent_doc_number] => 10622458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Self-aligned contact for vertical field effect transistor [patent_app_type] => utility [patent_app_number] => 15/599878 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9216 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599878 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599878
Self-aligned contact for vertical field effect transistor May 18, 2017 Issued
Array ( [id] => 12516567 [patent_doc_number] => 10002991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Light-emitting element [patent_app_type] => utility [patent_app_number] => 15/600179 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600179
Light-emitting element May 18, 2017 Issued
Array ( [id] => 11946014 [patent_doc_number] => 20170250165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'SEMICONDUCTOR PACKAGE ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/592488 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4341 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592488
Semiconductor package assembly May 10, 2017 Issued
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