Search

Leo B Tentoni

Examiner (ID: 11342, Phone: (571)272-1209 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1732, 1791, 1742, 1307
Total Applications
4287
Issued Applications
3378
Pending Applications
281
Abandoned Applications
662

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5340651 [patent_doc_number] => 20090179301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'FUSE HAVING CUTTING REGIONS AND FUSE SET STRUCTURE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/346587 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3678 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179301.pdf [firstpage_image] =>[orig_patent_app_number] => 12346587 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346587
FUSE HAVING CUTTING REGIONS AND FUSE SET STRUCTURE HAVING THE SAME Dec 29, 2008 Abandoned
Array ( [id] => 5275426 [patent_doc_number] => 20090127558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/345747 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4666 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127558.pdf [firstpage_image] =>[orig_patent_app_number] => 12345747 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345747
Display device Dec 29, 2008 Issued
Array ( [id] => 7527802 [patent_doc_number] => 08044395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Semiconductor memory apparatus for controlling pads and multi-chip package having the same' [patent_app_type] => utility [patent_app_number] => 12/346570 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4078 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/044/08044395.pdf [firstpage_image] =>[orig_patent_app_number] => 12346570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346570
Semiconductor memory apparatus for controlling pads and multi-chip package having the same Dec 29, 2008 Issued
Array ( [id] => 6392011 [patent_doc_number] => 20100163825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'FORMING PHASE CHANGE MEMORIES WITH A BREAKDOWN LAYER SANDWICHED BY PHASE CHANGE MEMORY MATERIAL' [patent_app_type] => utility [patent_app_number] => 12/346507 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3754 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20100163825.pdf [firstpage_image] =>[orig_patent_app_number] => 12346507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346507
Forming phase change memories with a breakdown layer sandwiched by phase change memory material Dec 29, 2008 Issued
Array ( [id] => 4586785 [patent_doc_number] => 07851856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'True CSP power MOSFET based on bottom-source LDMOS' [patent_app_type] => utility [patent_app_number] => 12/345467 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6219 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851856.pdf [firstpage_image] =>[orig_patent_app_number] => 12345467 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345467
True CSP power MOSFET based on bottom-source LDMOS Dec 28, 2008 Issued
Array ( [id] => 4639970 [patent_doc_number] => 08017997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via' [patent_app_type] => utility [patent_app_number] => 12/344697 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5338 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/017/08017997.pdf [firstpage_image] =>[orig_patent_app_number] => 12344697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344697
Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via Dec 28, 2008 Issued
Array ( [id] => 6599349 [patent_doc_number] => 20100032711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/344947 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5424 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20100032711.pdf [firstpage_image] =>[orig_patent_app_number] => 12344947 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344947
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Dec 28, 2008 Abandoned
Array ( [id] => 4474374 [patent_doc_number] => 07867808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Image sensor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/344538 [patent_app_country] => US [patent_app_date] => 2008-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2294 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/867/07867808.pdf [firstpage_image] =>[orig_patent_app_number] => 12344538 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344538
Image sensor and method for manufacturing the same Dec 27, 2008 Issued
Array ( [id] => 6280612 [patent_doc_number] => 20100155932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM' [patent_app_type] => utility [patent_app_number] => 12/343528 [patent_app_country] => US [patent_app_date] => 2008-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 11244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155932.pdf [firstpage_image] =>[orig_patent_app_number] => 12343528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/343528
Bonded semiconductor substrate including a cooling mechanism Dec 23, 2008 Issued
Array ( [id] => 4619600 [patent_doc_number] => 07999320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'SOI radio frequency switch with enhanced signal fidelity and electrical isolation' [patent_app_type] => utility [patent_app_number] => 12/342527 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 17873 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999320.pdf [firstpage_image] =>[orig_patent_app_number] => 12342527 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342527
SOI radio frequency switch with enhanced signal fidelity and electrical isolation Dec 22, 2008 Issued
Array ( [id] => 6280134 [patent_doc_number] => 20100155775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Design Structure and Method for an Electrostatic Discharge (ESD) Silicon Controlled Rectifier (SCR) Structure' [patent_app_type] => utility [patent_app_number] => 12/342228 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155775.pdf [firstpage_image] =>[orig_patent_app_number] => 12342228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342228
Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure Dec 22, 2008 Issued
Array ( [id] => 5340659 [patent_doc_number] => 20090179309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'Power semiconductor component with trench- type second contact region' [patent_app_type] => utility [patent_app_number] => 12/317338 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2891 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179309.pdf [firstpage_image] =>[orig_patent_app_number] => 12317338 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/317338
Power semiconductor component with trench-type second contact region Dec 21, 2008 Issued
Array ( [id] => 6280484 [patent_doc_number] => 20100155894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Fabricating Bipolar Junction Select Transistors For Semiconductor Memories' [patent_app_type] => utility [patent_app_number] => 12/341027 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1453 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155894.pdf [firstpage_image] =>[orig_patent_app_number] => 12341027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341027
Fabricating bipolar junction select transistors for semiconductor memories Dec 21, 2008 Issued
Array ( [id] => 4464165 [patent_doc_number] => 07935596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'HTO offset and BL trench process for memory device to improve device performance' [patent_app_type] => utility [patent_app_number] => 12/342008 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/935/07935596.pdf [firstpage_image] =>[orig_patent_app_number] => 12342008 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342008
HTO offset and BL trench process for memory device to improve device performance Dec 21, 2008 Issued
Array ( [id] => 5432099 [patent_doc_number] => 20090166685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/340027 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166685.pdf [firstpage_image] =>[orig_patent_app_number] => 12340027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340027
Semiconductor device and method of fabricating the same Dec 18, 2008 Issued
Array ( [id] => 7492244 [patent_doc_number] => 08030670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Multi-chip package for LED chip and multi-chip package LED device including the multi-chip package' [patent_app_type] => utility [patent_app_number] => 12/314738 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4215 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030670.pdf [firstpage_image] =>[orig_patent_app_number] => 12314738 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/314738
Multi-chip package for LED chip and multi-chip package LED device including the multi-chip package Dec 15, 2008 Issued
Array ( [id] => 6400974 [patent_doc_number] => 20100148346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'SEMICONDUCTOR DIE PACKAGE INCLUDING LOW STRESS CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 12/334127 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148346.pdf [firstpage_image] =>[orig_patent_app_number] => 12334127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334127
Semiconductor die package including low stress configuration Dec 11, 2008 Issued
Array ( [id] => 6410442 [patent_doc_number] => 20100140773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/332207 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5283 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140773.pdf [firstpage_image] =>[orig_patent_app_number] => 12332207 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332207
STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE Dec 9, 2008 Abandoned
Array ( [id] => 5419728 [patent_doc_number] => 20090146182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/331668 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20090146182.pdf [firstpage_image] =>[orig_patent_app_number] => 12331668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/331668
Nitride semiconductor device and method for fabricating the same Dec 9, 2008 Issued
Array ( [id] => 5352982 [patent_doc_number] => 20090184326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE DISPLAY SUBSTRATE AND DISPLAY APPARATUS HAVING THE DISPLAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/332117 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7339 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184326.pdf [firstpage_image] =>[orig_patent_app_number] => 12332117 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332117
Display substrate, method for manufacturing the display substrate and display apparatus having the display substrate Dec 9, 2008 Issued
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