Search

Leo B Tentoni

Examiner (ID: 106, Phone: (571)272-1209 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1732, 1307, 1791
Total Applications
4174
Issued Applications
3256
Pending Applications
267
Abandoned Applications
650

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16631619 [patent_doc_number] => 20210050272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => SEMICONDUCTOR PACKAGE SYSTEM AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/086932 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086932
SEMICONDUCTOR PACKAGE SYSTEM AND RELATED METHODS Nov 1, 2020 Pending
Array ( [id] => 19108690 [patent_doc_number] => 11961804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Size and efficiency of dies [patent_app_type] => utility [patent_app_number] => 17/083177 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083177
Size and efficiency of dies Oct 27, 2020 Issued
Array ( [id] => 16624893 [patent_doc_number] => 20210043546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/079736 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079736
Semiconductor device and method for manufacturing same Oct 25, 2020 Issued
Array ( [id] => 16631663 [patent_doc_number] => 20210050316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Interconnect Structure and Method of Forming Same [patent_app_type] => utility [patent_app_number] => 17/073533 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073533
Interconnect structure and method of forming same Oct 18, 2020 Issued
Array ( [id] => 18219559 [patent_doc_number] => 11594508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Redistribution lines having nano columns and method forming same [patent_app_type] => utility [patent_app_number] => 17/069539 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 7757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069539
Redistribution lines having nano columns and method forming same Oct 12, 2020 Issued
Array ( [id] => 16624910 [patent_doc_number] => 20210043563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS [patent_app_type] => utility [patent_app_number] => 17/068230 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068230
SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS Oct 11, 2020 Pending
Array ( [id] => 17056012 [patent_doc_number] => 20210265446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/060771 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060771
Display device Sep 30, 2020 Issued
Array ( [id] => 16732942 [patent_doc_number] => 20210100091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ORGANIC CIRCUIT CARRIER AND APPLICATION THEREOF IN POWER CONVERTERS AND IN VEHICLES [patent_app_type] => utility [patent_app_number] => 17/038040 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038040
ORGANIC CIRCUIT CARRIER AND APPLICATION THEREOF IN POWER CONVERTERS AND IN VEHICLES Sep 29, 2020 Pending
Array ( [id] => 18331829 [patent_doc_number] => 11637085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Semiconductor package and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/036465 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7066 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036465 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036465
Semiconductor package and method for fabricating the same Sep 28, 2020 Issued
Array ( [id] => 16560388 [patent_doc_number] => 20210005537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Sintered Metal Flip Chip Joints [patent_app_type] => utility [patent_app_number] => 17/027657 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027657
Sintered Metal Flip Chip Joints Sep 20, 2020 Pending
Array ( [id] => 18913026 [patent_doc_number] => 11876012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same [patent_app_type] => utility [patent_app_number] => 17/018596 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018596
Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same Sep 10, 2020 Issued
Array ( [id] => 17623228 [patent_doc_number] => 11342292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Bonding pad structure for memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/015223 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5371 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015223
Bonding pad structure for memory device and method of manufacturing the same Sep 8, 2020 Issued
Array ( [id] => 16516039 [patent_doc_number] => 20200395297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => LOCALIZED HIGH DENSITY SUBSTRATE ROUTING [patent_app_type] => utility [patent_app_number] => 17/009308 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009308
Localized high density substrate routing Aug 31, 2020 Issued
Array ( [id] => 17448350 [patent_doc_number] => 20220068855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE POLYMER LINER AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/004889 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004889
Semiconductor device structure with conductive polymer liner and method for forming the same Aug 26, 2020 Issued
Array ( [id] => 18175156 [patent_doc_number] => 11574873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/003639 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10217 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003639
Semiconductor package Aug 25, 2020 Issued
Array ( [id] => 16487778 [patent_doc_number] => 20200381387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => ALIGNMENT METHOD AND ALIGNMENT APPARATUS [patent_app_type] => utility [patent_app_number] => 16/998947 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998947
ALIGNMENT METHOD AND ALIGNMENT APPARATUS Aug 19, 2020 Pending
Array ( [id] => 18357861 [patent_doc_number] => 11646267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Thinned semiconductor package and related methods [patent_app_type] => utility [patent_app_number] => 16/941231 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5047 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941231
Thinned semiconductor package and related methods Jul 27, 2020 Issued
Array ( [id] => 16617290 [patent_doc_number] => 20210035943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => METHOD FOR MANUFACTURING AN ELECTRONIC CIRCUIT COMPONENT AND ELECTRONIC CIRCUIT COMPONENT [patent_app_type] => utility [patent_app_number] => 16/941406 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941406
METHOD FOR MANUFACTURING AN ELECTRONIC CIRCUIT COMPONENT AND ELECTRONIC CIRCUIT COMPONENT Jul 27, 2020 Abandoned
Array ( [id] => 16440441 [patent_doc_number] => 20200357768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/936433 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936433
Semiconductor package and manufacturing method thereof Jul 22, 2020 Issued
Array ( [id] => 18016354 [patent_doc_number] => 11508661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Integrated circuit and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 16/936249 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 37 [patent_no_of_words] => 25341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936249
Integrated circuit and method of manufacturing same Jul 21, 2020 Issued
Menu