Search

Leo B Tentoni

Examiner (ID: 106, Phone: (571)272-1209 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1732, 1307, 1791
Total Applications
4174
Issued Applications
3256
Pending Applications
267
Abandoned Applications
650

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17130363 [patent_doc_number] => 20210305132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES [patent_app_type] => utility [patent_app_number] => 16/828405 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828405
OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES Mar 23, 2020 Pending
Array ( [id] => 17978685 [patent_doc_number] => 11495557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/825713 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5608 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825713
Semiconductor device and method of manufacturing the same Mar 19, 2020 Issued
Array ( [id] => 17048041 [patent_doc_number] => 11101231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/819851 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819851
Semiconductor package and method of manufacturing the same Mar 15, 2020 Issued
Array ( [id] => 16316223 [patent_doc_number] => 20200294961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SHEET FOR SINTERING BONDING AND SHEET FOR SINTERING BONDING WITH BASE MATERIAL [patent_app_type] => utility [patent_app_number] => 16/816795 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/816795
SHEET FOR SINTERING BONDING AND SHEET FOR SINTERING BONDING WITH BASE MATERIAL Mar 11, 2020 Pending
Array ( [id] => 17708634 [patent_doc_number] => 20220208642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR APPARATUS AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/609906 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17609906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/609906
Semiconductor apparatus and electronic apparatus Feb 6, 2020 Issued
Array ( [id] => 17310129 [patent_doc_number] => 11211255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/783450 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 8639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/783450
Semiconductor structure Feb 5, 2020 Issued
Array ( [id] => 18804355 [patent_doc_number] => 11837519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Heatsink cutout and insulating through silicon vias to cut thermal cross-talk [patent_app_type] => utility [patent_app_number] => 16/783819 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 7898 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/783819
Heatsink cutout and insulating through silicon vias to cut thermal cross-talk Feb 5, 2020 Issued
Array ( [id] => 16746466 [patent_doc_number] => 10971467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Packaging method and package structure of fan-out chip [patent_app_type] => utility [patent_app_number] => 16/780167 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3763 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780167
Packaging method and package structure of fan-out chip Feb 2, 2020 Issued
Array ( [id] => 17810924 [patent_doc_number] => 20220262759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => ELECTRONIC APPARATUS, SEMICONDUCTOR DEVICE, INSULATING SHEET, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/427759 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/427759
ELECTRONIC APPARATUS, SEMICONDUCTOR DEVICE, INSULATING SHEET, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Feb 2, 2020 Pending
Array ( [id] => 18448380 [patent_doc_number] => 11683973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Use of thin film metal with stable native oxide for solder wetting control [patent_app_type] => utility [patent_app_number] => 16/778200 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 11475 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/778200
Use of thin film metal with stable native oxide for solder wetting control Jan 30, 2020 Issued
Array ( [id] => 18279979 [patent_doc_number] => 20230095451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/977807 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16977807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/977807
Display substrate and method for manufacturing the same and display device Nov 24, 2019 Issued
Array ( [id] => 17381053 [patent_doc_number] => 11239085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/687627 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687627
Semiconductor device and method for manufacturing the same Nov 17, 2019 Issued
Array ( [id] => 15625545 [patent_doc_number] => 20200083177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR [patent_app_type] => utility [patent_app_number] => 16/685699 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685699
Shielded package assemblies with integrated capacitor Nov 14, 2019 Issued
Array ( [id] => 15625527 [patent_doc_number] => 20200083168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => Dielectric Film for Semiconductor Fabrication [patent_app_type] => utility [patent_app_number] => 16/681556 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681556
Dielectric film for semiconductor fabrication Nov 11, 2019 Issued
Array ( [id] => 15597853 [patent_doc_number] => 20200075461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/678007 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678007
Semiconductor device and method for manufacturing same Nov 7, 2019 Issued
Array ( [id] => 15503815 [patent_doc_number] => 20200052096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SELF-ALIGNED CONTACT FOR VERTICAL FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/655589 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655589
Self-aligned contact for vertical field effect transistor Oct 16, 2019 Issued
Array ( [id] => 17638125 [patent_doc_number] => 11348859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Thermoelectric cooler (TEC) for spot cooling of 2.5D/3D IC packages [patent_app_type] => utility [patent_app_number] => 16/596100 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5291 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596100 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596100
Thermoelectric cooler (TEC) for spot cooling of 2.5D/3D IC packages Oct 7, 2019 Issued
Array ( [id] => 16752420 [patent_doc_number] => 20210104432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => PROCESSES FOR FORMING FULLY ALIGNED VIAS [patent_app_type] => utility [patent_app_number] => 16/592933 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592933
Semiconductor structure with fully aligned vias Oct 3, 2019 Issued
Array ( [id] => 17745677 [patent_doc_number] => 11393759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Alignment carrier for interconnect bridge assembly [patent_app_type] => utility [patent_app_number] => 16/593489 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 7719 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593489 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593489
Alignment carrier for interconnect bridge assembly Oct 3, 2019 Issued
Array ( [id] => 16119831 [patent_doc_number] => 20200211938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/593300 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593300 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593300
SEMICONDUCTOR PACKAGE Oct 3, 2019 Abandoned
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