| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[id] => 3611657
[patent_doc_number] => 05565384
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Self-aligned via using low permittivity dielectric'
[patent_app_type] => 1
[patent_app_number] => 8/234100
[patent_app_country] => US
[patent_app_date] => 1994-04-28
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[firstpage_image] =>[orig_patent_app_number] => 234100
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/234100 | Self-aligned via using low permittivity dielectric | Apr 27, 1994 | Issued |
Array
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[id] => 3493374
[patent_doc_number] => 05508207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Method of annealing a semiconductor wafer in a hydrogen atmosphere to desorb surface contaminants'
[patent_app_type] => 1
[patent_app_number] => 8/199170
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[firstpage_image] =>[orig_patent_app_number] => 199170
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/199170 | Method of annealing a semiconductor wafer in a hydrogen atmosphere to desorb surface contaminants | Apr 25, 1994 | Issued |
Array
(
[id] => 3111875
[patent_doc_number] => 05395771
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'Graded implantation of oxygen and/or nitrogen constituents to define buried isolation region in semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/232880
[patent_app_country] => US
[patent_app_date] => 1994-04-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/395/05395771.pdf
[firstpage_image] =>[orig_patent_app_number] => 232880
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/232880 | Graded implantation of oxygen and/or nitrogen constituents to define buried isolation region in semiconductor devices | Apr 24, 1994 | Issued |
| 08/227930 | METHOD FOR FORMING A FERROELECTRIC MATERIAL FILM BY THE SOL-GEL METHOD, ALONG WITH A PROCESS FOR THE PRODUCTION OF A CAPACITOR AND ITS RAW MATERIAL SOLUTION | Apr 14, 1994 | Abandoned |
| 08/224914 | EXTENDED DRAIN RESURF LATERAL DMOS DEVICES | Apr 7, 1994 | Abandoned |
Array
(
[id] => 3695502
[patent_doc_number] => 05595916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Silicon oxide film evaluation method'
[patent_app_type] => 1
[patent_app_number] => 8/219550
[patent_app_country] => US
[patent_app_date] => 1994-03-29
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[firstpage_image] =>[orig_patent_app_number] => 219550
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/219550 | Silicon oxide film evaluation method | Mar 28, 1994 | Issued |
Array
(
[id] => 3574215
[patent_doc_number] => 05523240
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Method of manufacturing a thin film transistor with a halogen doped blocking layer'
[patent_app_type] => 1
[patent_app_number] => 8/219286
[patent_app_country] => US
[patent_app_date] => 1994-03-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/523/05523240.pdf
[firstpage_image] =>[orig_patent_app_number] => 219286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/219286 | Method of manufacturing a thin film transistor with a halogen doped blocking layer | Mar 27, 1994 | Issued |
| 08/218474 | METHOD OF FORMING IMPROVED CONTACTS FROM POLYSILICON TO SILICON OR OTHER POLYSILICON LAYERS | Mar 23, 1994 | Abandoned |
| 08/216108 | TRANSISTOR AND METHOD OF FORMING THE SAME | Mar 20, 1994 | Abandoned |
| 08/210764 | TRANSISTOR AND METHOD OF FORMING THE SAME | Mar 20, 1994 | Abandoned |
Array
(
[id] => 3474532
[patent_doc_number] => 05427974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-27
[patent_title] => 'Method for forming a capacitor in a DRAM cell using a rough overlayer of tungsten'
[patent_app_type] => 1
[patent_app_number] => 8/214602
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[patent_app_date] => 1994-03-18
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[firstpage_image] =>[orig_patent_app_number] => 214602
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/214602 | Method for forming a capacitor in a DRAM cell using a rough overlayer of tungsten | Mar 17, 1994 | Issued |
Array
(
[id] => 3461120
[patent_doc_number] => 05468680
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Method of making a three-terminal fuse'
[patent_app_type] => 1
[patent_app_number] => 8/210344
[patent_app_country] => US
[patent_app_date] => 1994-03-18
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[pdf_file] => patents/05/468/05468680.pdf
[firstpage_image] =>[orig_patent_app_number] => 210344
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/210344 | Method of making a three-terminal fuse | Mar 17, 1994 | Issued |
Array
(
[id] => 3101973
[patent_doc_number] => 05447873
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-05
[patent_title] => 'Method of making a universal quantum dot logic cell'
[patent_app_type] => 1
[patent_app_number] => 8/214084
[patent_app_country] => US
[patent_app_date] => 1994-03-16
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 214084
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/214084 | Method of making a universal quantum dot logic cell | Mar 15, 1994 | Issued |
Array
(
[id] => 3581330
[patent_doc_number] => 05580800
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Method of patterning aluminum containing group IIIb Element'
[patent_app_type] => 1
[patent_app_number] => 8/213060
[patent_app_country] => US
[patent_app_date] => 1994-03-15
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[pdf_file] => patents/05/580/05580800.pdf
[firstpage_image] =>[orig_patent_app_number] => 213060
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/213060 | Method of patterning aluminum containing group IIIb Element | Mar 14, 1994 | Issued |
Array
(
[id] => 3552105
[patent_doc_number] => 05492853
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/209584
[patent_app_country] => US
[patent_app_date] => 1994-03-11
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[firstpage_image] =>[orig_patent_app_number] => 209584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/209584 | Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device | Mar 10, 1994 | Issued |
| 08/199956 | PROCESS FOR FABRICATING ELECTRONIC CIRCUITS | Feb 21, 1994 | Abandoned |
Array
(
[id] => 3444119
[patent_doc_number] => 05420059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Method of making a high performance MESFET with multiple quantum wells'
[patent_app_type] => 1
[patent_app_number] => 8/198938
[patent_app_country] => US
[patent_app_date] => 1994-02-18
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/198938 | Method of making a high performance MESFET with multiple quantum wells | Feb 17, 1994 | Issued |
Array
(
[id] => 3587772
[patent_doc_number] => 05516720
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Stress relaxation in dielectric before metallization'
[patent_app_type] => 1
[patent_app_number] => 8/195090
[patent_app_country] => US
[patent_app_date] => 1994-02-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/516/05516720.pdf
[firstpage_image] =>[orig_patent_app_number] => 195090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/195090 | Stress relaxation in dielectric before metallization | Feb 13, 1994 | Issued |
| 08/194596 | METHOD OF MANUFACTURING INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR DEVICE | Feb 9, 1994 | Abandoned |
| 08/229450 | METHODS FOR IMPROVING SEMICONDUCTOR PROCESSING | Jan 26, 1994 | Abandoned |