Search

Leon Radomsky

Examiner (ID: 2961)

Most Active Art Unit
1104
Art Unit(s)
1104, 2813, 1763
Total Applications
270
Issued Applications
204
Pending Applications
8
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3773897 [patent_doc_number] => 05817550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method for formation of thin film transistors on plastic substrates' [patent_app_type] => 1 [patent_app_number] => 8/611318 [patent_app_country] => US [patent_app_date] => 1996-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3588 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817550.pdf [firstpage_image] =>[orig_patent_app_number] => 611318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611318
Method for formation of thin film transistors on plastic substrates Mar 4, 1996 Issued
Array ( [id] => 3694379 [patent_doc_number] => 05661049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Stress relaxation in dielectric before metallization' [patent_app_type] => 1 [patent_app_number] => 8/609256 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3801 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661049.pdf [firstpage_image] =>[orig_patent_app_number] => 609256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/609256
Stress relaxation in dielectric before metallization Feb 28, 1996 Issued
Array ( [id] => 3730998 [patent_doc_number] => 05665632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Stress relaxation in dielectric before metalization' [patent_app_type] => 1 [patent_app_number] => 8/608071 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3798 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665632.pdf [firstpage_image] =>[orig_patent_app_number] => 608071 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608071
Stress relaxation in dielectric before metalization Feb 27, 1996 Issued
Array ( [id] => 3884181 [patent_doc_number] => 05776790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'C4 Pb/Sn evaporation process' [patent_app_type] => 1 [patent_app_number] => 8/608162 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1718 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776790.pdf [firstpage_image] =>[orig_patent_app_number] => 608162 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608162
C4 Pb/Sn evaporation process Feb 27, 1996 Issued
Array ( [id] => 3646902 [patent_doc_number] => 05629216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method for producing semiconductor wafers with low light scattering anomalies' [patent_app_type] => 1 [patent_app_number] => 8/607626 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3178 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629216.pdf [firstpage_image] =>[orig_patent_app_number] => 607626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607626
Method for producing semiconductor wafers with low light scattering anomalies Feb 26, 1996 Issued
Array ( [id] => 3813844 [patent_doc_number] => 05789318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Use of titanium hydride in integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 8/606164 [patent_app_country] => US [patent_app_date] => 1996-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3957 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789318.pdf [firstpage_image] =>[orig_patent_app_number] => 606164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606164
Use of titanium hydride in integrated circuit fabrication Feb 22, 1996 Issued
Array ( [id] => 3781800 [patent_doc_number] => 05821138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method of manufacturing a semiconductor device using a metal which promotes crystallization of silicon and substrate bonding' [patent_app_type] => 1 [patent_app_number] => 8/602324 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 11418 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821138.pdf [firstpage_image] =>[orig_patent_app_number] => 602324 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/602324
Method of manufacturing a semiconductor device using a metal which promotes crystallization of silicon and substrate bonding Feb 15, 1996 Issued
Array ( [id] => 3827980 [patent_doc_number] => 05739043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method for producing a substrate having crystalline silicon nuclei for forming a polysilicon thin film' [patent_app_type] => 1 [patent_app_number] => 8/599652 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8019 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739043.pdf [firstpage_image] =>[orig_patent_app_number] => 599652 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599652
Method for producing a substrate having crystalline silicon nuclei for forming a polysilicon thin film Feb 11, 1996 Issued
Array ( [id] => 3847572 [patent_doc_number] => 05719078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Method for making a thin film transistor panel used in a liquid crystal display having a completely self-aligned thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/600054 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 2122 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719078.pdf [firstpage_image] =>[orig_patent_app_number] => 600054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600054
Method for making a thin film transistor panel used in a liquid crystal display having a completely self-aligned thin film transistor Feb 11, 1996 Issued
08/599267 ISOLATED VERTICAL PNP TRANSISTOR WITHOUT REQUIRED BURIED LAYER Feb 8, 1996 Abandoned
Array ( [id] => 3767932 [patent_doc_number] => 05773325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method of making a variable concentration SiON gate insulating film' [patent_app_type] => 1 [patent_app_number] => 8/598279 [patent_app_country] => US [patent_app_date] => 1996-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 6703 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773325.pdf [firstpage_image] =>[orig_patent_app_number] => 598279 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/598279
Method of making a variable concentration SiON gate insulating film Feb 7, 1996 Issued
Array ( [id] => 3836335 [patent_doc_number] => 05846844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method for producing group III nitride compound semiconductor substrates using ZnO release layers' [patent_app_type] => 1 [patent_app_number] => 8/598134 [patent_app_country] => US [patent_app_date] => 1996-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1891 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846844.pdf [firstpage_image] =>[orig_patent_app_number] => 598134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/598134
Method for producing group III nitride compound semiconductor substrates using ZnO release layers Feb 6, 1996 Issued
Array ( [id] => 3836495 [patent_doc_number] => 05846854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Electrical circuits with very high conductivity and high fineness, processes for fabricating them, and devices comprising them' [patent_app_type] => 1 [patent_app_number] => 8/581620 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 35 [patent_no_of_words] => 8034 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846854.pdf [firstpage_image] =>[orig_patent_app_number] => 581620 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581620
Electrical circuits with very high conductivity and high fineness, processes for fabricating them, and devices comprising them Jan 17, 1996 Issued
Array ( [id] => 3832082 [patent_doc_number] => 05814529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/585916 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 27 [patent_no_of_words] => 4949 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814529.pdf [firstpage_image] =>[orig_patent_app_number] => 585916 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585916
Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor Jan 15, 1996 Issued
Array ( [id] => 3687324 [patent_doc_number] => 05691217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Semiconductor processing method of forming a pair of field effect transistors having different thickness gate dielectric layers' [patent_app_type] => 1 [patent_app_number] => 8/582446 [patent_app_country] => US [patent_app_date] => 1996-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2560 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691217.pdf [firstpage_image] =>[orig_patent_app_number] => 582446 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/582446
Semiconductor processing method of forming a pair of field effect transistors having different thickness gate dielectric layers Jan 2, 1996 Issued
Array ( [id] => 3742826 [patent_doc_number] => 05801087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method of forming improved contacts from polysilicon to siliconor other polysilicon layers' [patent_app_type] => 1 [patent_app_number] => 8/582310 [patent_app_country] => US [patent_app_date] => 1996-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2623 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801087.pdf [firstpage_image] =>[orig_patent_app_number] => 582310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/582310
Method of forming improved contacts from polysilicon to siliconor other polysilicon layers Jan 2, 1996 Issued
Array ( [id] => 3849209 [patent_doc_number] => 05766989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method for forming polycrystalline thin film and method for fabricating thin-film transistor' [patent_app_type] => 1 [patent_app_number] => 8/579140 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 7953 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/766/05766989.pdf [firstpage_image] =>[orig_patent_app_number] => 579140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579140
Method for forming polycrystalline thin film and method for fabricating thin-film transistor Dec 26, 1995 Issued
Array ( [id] => 3786195 [patent_doc_number] => 05840620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures' [patent_app_type] => 1 [patent_app_number] => 8/577851 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1625 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/840/05840620.pdf [firstpage_image] =>[orig_patent_app_number] => 577851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/577851
Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures Dec 21, 1995 Issued
Array ( [id] => 3828183 [patent_doc_number] => 05739058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method to control threshold voltage by modifying implant dosage using variable aperture dopant implants' [patent_app_type] => 1 [patent_app_number] => 8/572020 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4153 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739058.pdf [firstpage_image] =>[orig_patent_app_number] => 572020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572020
Method to control threshold voltage by modifying implant dosage using variable aperture dopant implants Dec 13, 1995 Issued
Array ( [id] => 3832224 [patent_doc_number] => 05712203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Process for fabricating read-only memory cells using removable barrier strips' [patent_app_type] => 1 [patent_app_number] => 8/570340 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2502 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712203.pdf [firstpage_image] =>[orig_patent_app_number] => 570340 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/570340
Process for fabricating read-only memory cells using removable barrier strips Dec 10, 1995 Issued
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