| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05739067
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[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer'
[patent_app_type] => 1
[patent_app_number] => 8/568992
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[patent_app_date] => 1995-12-07
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Array
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[id] => 3656415
[patent_doc_number] => 05658807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Methods of forming conductive polysilicon lines and bottom gated thin film transistors'
[patent_app_type] => 1
[patent_app_number] => 8/566653
[patent_app_country] => US
[patent_app_date] => 1995-12-04
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[firstpage_image] =>[orig_patent_app_number] => 566653
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566653 | Methods of forming conductive polysilicon lines and bottom gated thin film transistors | Dec 3, 1995 | Issued |
Array
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[id] => 3619890
[patent_doc_number] => 05688704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Integrated circuit fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/565286
[patent_app_country] => US
[patent_app_date] => 1995-11-30
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[firstpage_image] =>[orig_patent_app_number] => 565286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/565286 | Integrated circuit fabrication | Nov 29, 1995 | Issued |
Array
(
[id] => 3656453
[patent_doc_number] => 05658810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Method of making a sensor for determining a ratio of materials in a mixture'
[patent_app_type] => 1
[patent_app_number] => 8/563432
[patent_app_country] => US
[patent_app_date] => 1995-11-24
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/563432 | Method of making a sensor for determining a ratio of materials in a mixture | Nov 23, 1995 | Issued |
Array
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[id] => 3769690
[patent_doc_number] => 05756364
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Laser processing method of semiconductor device using a catalyst'
[patent_app_type] => 1
[patent_app_number] => 8/562274
[patent_app_country] => US
[patent_app_date] => 1995-11-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 562274
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/562274 | Laser processing method of semiconductor device using a catalyst | Nov 21, 1995 | Issued |
| 08/555648 | METHOD OF FORMING A SPACER | Nov 12, 1995 | Abandoned |
| 08/556642 | TRANSISTOR AND METHOD OF FORMING THE SAME | Nov 12, 1995 | Abandoned |
Array
(
[id] => 3756939
[patent_doc_number] => 05721144
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[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Method of making trimmable modular MOSFETs for high aspect ratio applications'
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Array
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[patent_doc_number] => 05726081
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[patent_issue_date] => 1998-03-10
[patent_title] => 'Method of fabricating metal contact of ultra-large-scale integration metal-oxide semiconductor field effect transistor with silicon-on-insulator structure'
[patent_app_type] => 1
[patent_app_number] => 8/544659
[patent_app_country] => US
[patent_app_date] => 1995-10-18
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[pdf_file] => patents/05/726/05726081.pdf
[firstpage_image] =>[orig_patent_app_number] => 544659
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544659 | Method of fabricating metal contact of ultra-large-scale integration metal-oxide semiconductor field effect transistor with silicon-on-insulator structure | Oct 17, 1995 | Issued |
Array
(
[id] => 4046309
[patent_doc_number] => 05869362
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[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/544004
[patent_app_country] => US
[patent_app_date] => 1995-10-17
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[pdf_file] => patents/05/869/05869362.pdf
[firstpage_image] =>[orig_patent_app_number] => 544004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544004 | Method of manufacturing semiconductor device | Oct 16, 1995 | Issued |
Array
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[id] => 3726699
[patent_doc_number] => 05670388
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Method of making contacted body silicon-on-insulator field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/542592
[patent_app_country] => US
[patent_app_date] => 1995-10-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542592 | Method of making contacted body silicon-on-insulator field effect transistor | Oct 12, 1995 | Issued |
Array
(
[id] => 3876855
[patent_doc_number] => 05728608
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Tapered dielectric etch in semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/541066
[patent_app_country] => US
[patent_app_date] => 1995-10-11
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[firstpage_image] =>[orig_patent_app_number] => 541066
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541066 | Tapered dielectric etch in semiconductor devices | Oct 10, 1995 | Issued |
| 08/536238 | INTERFACE BETWEEN TITANIUM AND ALUMINUM-ALLOY IN METAL STACK FOR INTEGRATED CIRCUIT | Sep 28, 1995 | Abandoned |
| 08/533716 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME | Sep 25, 1995 | Abandoned |
Array
(
[id] => 3885730
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Method of making a high voltage planar edge termination structure'
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[patent_app_date] => 1995-09-18
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[firstpage_image] =>[orig_patent_app_number] => 529384
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/529384 | Method of making a high voltage planar edge termination structure | Sep 17, 1995 | Issued |
Array
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[patent_issue_date] => 1997-12-09
[patent_title] => 'Method of producing semiconductor device with a buried layer'
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Array
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[patent_title] => 'Method of fabricating thin film transistor with supplementary gates'
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Array
(
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[patent_issue_date] => 1997-01-14
[patent_title] => 'Process for forming a semiconductor device including conductive members'
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[firstpage_image] =>[orig_patent_app_number] => 523174
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/523174 | Process for forming a semiconductor device including conductive members | Sep 4, 1995 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 521720
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/521720 | Process for reducing halogen concentration in a material layer during semiconductor device fabrication | Aug 30, 1995 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method for manufacturing a semiconductor device using a silicon nitride mask'
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[firstpage_image] =>[orig_patent_app_number] => 518364
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518364 | Method for manufacturing a semiconductor device using a silicon nitride mask | Aug 22, 1995 | Issued |