Search

Leon Radomsky

Examiner (ID: 7815)

Most Active Art Unit
1104
Art Unit(s)
1104, 2813, 1763
Total Applications
270
Issued Applications
204
Pending Applications
8
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3828303 [patent_doc_number] => 05739067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer' [patent_app_type] => 1 [patent_app_number] => 8/568992 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5406 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739067.pdf [firstpage_image] =>[orig_patent_app_number] => 568992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568992
Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer Dec 6, 1995 Issued
Array ( [id] => 3656415 [patent_doc_number] => 05658807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Methods of forming conductive polysilicon lines and bottom gated thin film transistors' [patent_app_type] => 1 [patent_app_number] => 8/566653 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2526 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/658/05658807.pdf [firstpage_image] =>[orig_patent_app_number] => 566653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566653
Methods of forming conductive polysilicon lines and bottom gated thin film transistors Dec 3, 1995 Issued
Array ( [id] => 3619890 [patent_doc_number] => 05688704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 8/565286 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1293 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/688/05688704.pdf [firstpage_image] =>[orig_patent_app_number] => 565286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565286
Integrated circuit fabrication Nov 29, 1995 Issued
Array ( [id] => 3656453 [patent_doc_number] => 05658810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Method of making a sensor for determining a ratio of materials in a mixture' [patent_app_type] => 1 [patent_app_number] => 8/563432 [patent_app_country] => US [patent_app_date] => 1995-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1891 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/658/05658810.pdf [firstpage_image] =>[orig_patent_app_number] => 563432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563432
Method of making a sensor for determining a ratio of materials in a mixture Nov 23, 1995 Issued
Array ( [id] => 3769690 [patent_doc_number] => 05756364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Laser processing method of semiconductor device using a catalyst' [patent_app_type] => 1 [patent_app_number] => 8/562274 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7268 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/756/05756364.pdf [firstpage_image] =>[orig_patent_app_number] => 562274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562274
Laser processing method of semiconductor device using a catalyst Nov 21, 1995 Issued
08/555648 METHOD OF FORMING A SPACER Nov 12, 1995 Abandoned
08/556642 TRANSISTOR AND METHOD OF FORMING THE SAME Nov 12, 1995 Abandoned
Array ( [id] => 3756939 [patent_doc_number] => 05721144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method of making trimmable modular MOSFETs for high aspect ratio applications' [patent_app_type] => 1 [patent_app_number] => 8/547180 [patent_app_country] => US [patent_app_date] => 1995-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2030 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721144.pdf [firstpage_image] =>[orig_patent_app_number] => 547180 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547180
Method of making trimmable modular MOSFETs for high aspect ratio applications Oct 23, 1995 Issued
Array ( [id] => 3791612 [patent_doc_number] => 05726081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Method of fabricating metal contact of ultra-large-scale integration metal-oxide semiconductor field effect transistor with silicon-on-insulator structure' [patent_app_type] => 1 [patent_app_number] => 8/544659 [patent_app_country] => US [patent_app_date] => 1995-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 1530 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726081.pdf [firstpage_image] =>[orig_patent_app_number] => 544659 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544659
Method of fabricating metal contact of ultra-large-scale integration metal-oxide semiconductor field effect transistor with silicon-on-insulator structure Oct 17, 1995 Issued
Array ( [id] => 4046309 [patent_doc_number] => 05869362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/544004 [patent_app_country] => US [patent_app_date] => 1995-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5685 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869362.pdf [firstpage_image] =>[orig_patent_app_number] => 544004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544004
Method of manufacturing semiconductor device Oct 16, 1995 Issued
Array ( [id] => 3726699 [patent_doc_number] => 05670388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method of making contacted body silicon-on-insulator field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/542592 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 6465 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670388.pdf [firstpage_image] =>[orig_patent_app_number] => 542592 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542592
Method of making contacted body silicon-on-insulator field effect transistor Oct 12, 1995 Issued
Array ( [id] => 3876855 [patent_doc_number] => 05728608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Tapered dielectric etch in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/541066 [patent_app_country] => US [patent_app_date] => 1995-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2808 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728608.pdf [firstpage_image] =>[orig_patent_app_number] => 541066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/541066
Tapered dielectric etch in semiconductor devices Oct 10, 1995 Issued
08/536238 INTERFACE BETWEEN TITANIUM AND ALUMINUM-ALLOY IN METAL STACK FOR INTEGRATED CIRCUIT Sep 28, 1995 Abandoned
08/533716 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME Sep 25, 1995 Abandoned
Array ( [id] => 3885730 [patent_doc_number] => 05714396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method of making a high voltage planar edge termination structure' [patent_app_type] => 1 [patent_app_number] => 8/529384 [patent_app_country] => US [patent_app_date] => 1995-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2106 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714396.pdf [firstpage_image] =>[orig_patent_app_number] => 529384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/529384
Method of making a high voltage planar edge termination structure Sep 17, 1995 Issued
Array ( [id] => 3686586 [patent_doc_number] => 05696004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Method of producing semiconductor device with a buried layer' [patent_app_type] => 1 [patent_app_number] => 8/527093 [patent_app_country] => US [patent_app_date] => 1995-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2887 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696004.pdf [firstpage_image] =>[orig_patent_app_number] => 527093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/527093
Method of producing semiconductor device with a buried layer Sep 11, 1995 Issued
Array ( [id] => 3729946 [patent_doc_number] => 05693549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method of fabricating thin film transistor with supplementary gates' [patent_app_type] => 1 [patent_app_number] => 8/527008 [patent_app_country] => US [patent_app_date] => 1995-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4107 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693549.pdf [firstpage_image] =>[orig_patent_app_number] => 527008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/527008
Method of fabricating thin film transistor with supplementary gates Sep 11, 1995 Issued
Array ( [id] => 3621421 [patent_doc_number] => 05593919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Process for forming a semiconductor device including conductive members' [patent_app_type] => 1 [patent_app_number] => 8/523174 [patent_app_country] => US [patent_app_date] => 1995-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3811 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593919.pdf [firstpage_image] =>[orig_patent_app_number] => 523174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/523174
Process for forming a semiconductor device including conductive members Sep 4, 1995 Issued
Array ( [id] => 3804722 [patent_doc_number] => 05830802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Process for reducing halogen concentration in a material layer during semiconductor device fabrication' [patent_app_type] => 1 [patent_app_number] => 8/521720 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1901 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/830/05830802.pdf [firstpage_image] =>[orig_patent_app_number] => 521720 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521720
Process for reducing halogen concentration in a material layer during semiconductor device fabrication Aug 30, 1995 Issued
Array ( [id] => 3729817 [patent_doc_number] => 05693541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method for manufacturing a semiconductor device using a silicon nitride mask' [patent_app_type] => 1 [patent_app_number] => 8/518364 [patent_app_country] => US [patent_app_date] => 1995-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693541.pdf [firstpage_image] =>[orig_patent_app_number] => 518364 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/518364
Method for manufacturing a semiconductor device using a silicon nitride mask Aug 22, 1995 Issued
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