
Leon Radomsky
Examiner (ID: 13067)
| Most Active Art Unit | 1104 |
| Art Unit(s) | 1104, 2813, 1763 |
| Total Applications | 270 |
| Issued Applications | 204 |
| Pending Applications | 8 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3824312
[patent_doc_number] => 05731220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Method of making barium strontium titanate (BST) thin film by erbium donor doping'
[patent_app_type] => 1
[patent_app_number] => 8/474614
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 5
[patent_no_of_words] => 3237
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731220.pdf
[firstpage_image] =>[orig_patent_app_number] => 474614
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/474614 | Method of making barium strontium titanate (BST) thin film by erbium donor doping | Jun 6, 1995 | Issued |
Array
(
[id] => 3714904
[patent_doc_number] => 05616515
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Silicon oxide germanium resonant tunneling'
[patent_app_type] => 1
[patent_app_number] => 8/484464
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 29
[patent_no_of_words] => 4253
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[patent_words_short_claim] => 78
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/616/05616515.pdf
[firstpage_image] =>[orig_patent_app_number] => 484464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484464 | Silicon oxide germanium resonant tunneling | Jun 6, 1995 | Issued |
Array
(
[id] => 3722673
[patent_doc_number] => 05672519
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Method of fabricating solid state image sensing elements'
[patent_app_type] => 1
[patent_app_number] => 8/484980
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3375
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 117
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/672/05672519.pdf
[firstpage_image] =>[orig_patent_app_number] => 484980
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484980 | Method of fabricating solid state image sensing elements | Jun 5, 1995 | Issued |
Array
(
[id] => 3695611
[patent_doc_number] => 05595923
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Method of forming a thin film transistor'
[patent_app_type] => 1
[patent_app_number] => 8/467986
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7127
[patent_no_of_claims] => 16
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/595/05595923.pdf
[firstpage_image] =>[orig_patent_app_number] => 467986
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/467986 | Method of forming a thin film transistor | Jun 5, 1995 | Issued |
Array
(
[id] => 3694969
[patent_doc_number] => 05661091
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Method of manufacturing a semiconductor device having PN junctions separated by depressions'
[patent_app_type] => 1
[patent_app_number] => 8/479018
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5862
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/661/05661091.pdf
[firstpage_image] =>[orig_patent_app_number] => 479018
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/479018 | Method of manufacturing a semiconductor device having PN junctions separated by depressions | Jun 5, 1995 | Issued |
Array
(
[id] => 3700973
[patent_doc_number] => 05674758
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Silicon on insulator achieved using electrochemical etching'
[patent_app_type] => 1
[patent_app_number] => 8/484062
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[patent_no_of_words] => 12341
[patent_no_of_claims] => 25
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[pdf_file] => patents/05/674/05674758.pdf
[firstpage_image] =>[orig_patent_app_number] => 484062
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484062 | Silicon on insulator achieved using electrochemical etching | Jun 5, 1995 | Issued |
| 08/462742 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SAME | Jun 4, 1995 | Abandoned |
| 08/463550 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING THIN-FILM RESISTOR | Jun 4, 1995 | Abandoned |
Array
(
[id] => 3585907
[patent_doc_number] => 05552328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Method of fabrication of porous silicon light emitting diode arrays'
[patent_app_type] => 1
[patent_app_number] => 8/463162
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 3752
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/552/05552328.pdf
[firstpage_image] =>[orig_patent_app_number] => 463162
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463162 | Method of fabrication of porous silicon light emitting diode arrays | Jun 4, 1995 | Issued |
Array
(
[id] => 3686698
[patent_doc_number] => 05696013
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Method of manufacturing semiconductor device having unit circuit-blocks'
[patent_app_type] => 1
[patent_app_number] => 8/463928
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 24
[patent_no_of_words] => 4290
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[pdf_file] => patents/05/696/05696013.pdf
[firstpage_image] =>[orig_patent_app_number] => 463928
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463928 | Method of manufacturing semiconductor device having unit circuit-blocks | Jun 4, 1995 | Issued |
Array
(
[id] => 3771661
[patent_doc_number] => 05807772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Method for forming semiconductor device with bottom gate connected to source or drain'
[patent_app_type] => 1
[patent_app_number] => 8/463060
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 6953
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[pdf_file] => patents/05/807/05807772.pdf
[firstpage_image] =>[orig_patent_app_number] => 463060
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463060 | Method for forming semiconductor device with bottom gate connected to source or drain | Jun 4, 1995 | Issued |
Array
(
[id] => 3681617
[patent_doc_number] => 05633176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Method of producing a semiconductor device for a light valve'
[patent_app_type] => 1
[patent_app_number] => 8/463687
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 9895
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[pdf_file] => patents/05/633/05633176.pdf
[firstpage_image] =>[orig_patent_app_number] => 463687
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463687 | Method of producing a semiconductor device for a light valve | Jun 4, 1995 | Issued |
Array
(
[id] => 3694539
[patent_doc_number] => 05618739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Method of making light valve device using semiconductive composite substrate'
[patent_app_type] => 1
[patent_app_number] => 8/459834
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 15826
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[pdf_file] => patents/05/618/05618739.pdf
[firstpage_image] =>[orig_patent_app_number] => 459834
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/459834 | Method of making light valve device using semiconductive composite substrate | Jun 1, 1995 | Issued |
Array
(
[id] => 3876578
[patent_doc_number] => 05728591
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Process for manufacturing light valve device using semiconductive composite substrate'
[patent_app_type] => 1
[patent_app_number] => 8/460536
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[pdf_file] => patents/05/728/05728591.pdf
[firstpage_image] =>[orig_patent_app_number] => 460536
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/460536 | Process for manufacturing light valve device using semiconductive composite substrate | Jun 1, 1995 | Issued |
Array
(
[id] => 3729864
[patent_doc_number] => 05635410
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-03
[patent_title] => 'Bias temperature treatment method'
[patent_app_type] => 1
[patent_app_number] => 8/458918
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/05/635/05635410.pdf
[firstpage_image] =>[orig_patent_app_number] => 458918
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458918 | Bias temperature treatment method | Jun 1, 1995 | Issued |
| 08/460560 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | Jun 1, 1995 | Abandoned |
Array
(
[id] => 3690674
[patent_doc_number] => 05604137
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'Method for forming a multilayer integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/460632
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/604/05604137.pdf
[firstpage_image] =>[orig_patent_app_number] => 460632
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/460632 | Method for forming a multilayer integrated circuit | Jun 1, 1995 | Issued |
Array
(
[id] => 3838527
[patent_doc_number] => 05744372
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Fabrication of complementary field-effect transistors each having multi-part channel'
[patent_app_type] => 1
[patent_app_number] => 8/456454
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/744/05744372.pdf
[firstpage_image] =>[orig_patent_app_number] => 456454
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/456454 | Fabrication of complementary field-effect transistors each having multi-part channel | May 31, 1995 | Issued |
Array
(
[id] => 3768701
[patent_doc_number] => 05849611
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Method for forming a taper shaped contact hole by oxidizing a wiring'
[patent_app_type] => 1
[patent_app_number] => 8/455156
[patent_app_country] => US
[patent_app_date] => 1995-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[pdf_file] => patents/05/849/05849611.pdf
[firstpage_image] =>[orig_patent_app_number] => 455156
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/455156 | Method for forming a taper shaped contact hole by oxidizing a wiring | May 30, 1995 | Issued |
Array
(
[id] => 3693918
[patent_doc_number] => 05650340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Method of making asymmetric low power MOS devices'
[patent_app_type] => 1
[patent_app_number] => 8/456048
[patent_app_country] => US
[patent_app_date] => 1995-05-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/650/05650340.pdf
[firstpage_image] =>[orig_patent_app_number] => 456048
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/456048 | Method of making asymmetric low power MOS devices | May 30, 1995 | Issued |