Search

Leon Radomsky

Examiner (ID: 13067)

Most Active Art Unit
1104
Art Unit(s)
1104, 2813, 1763
Total Applications
270
Issued Applications
204
Pending Applications
8
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3570632 [patent_doc_number] => 05538906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Process for producing mask ROM' [patent_app_type] => 1 [patent_app_number] => 8/380710 [patent_app_country] => US [patent_app_date] => 1995-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 5246 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/538/05538906.pdf [firstpage_image] =>[orig_patent_app_number] => 380710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/380710
Process for producing mask ROM Jan 29, 1995 Issued
Array ( [id] => 3647276 [patent_doc_number] => 05629242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Process for planarizing surface of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/372942 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 74 [patent_no_of_words] => 24018 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629242.pdf [firstpage_image] =>[orig_patent_app_number] => 372942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/372942
Process for planarizing surface of a semiconductor device Jan 16, 1995 Issued
Array ( [id] => 3660266 [patent_doc_number] => 05656521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Method of erasing UPROM transistors' [patent_app_type] => 1 [patent_app_number] => 8/371704 [patent_app_country] => US [patent_app_date] => 1995-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2624 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656521.pdf [firstpage_image] =>[orig_patent_app_number] => 371704 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/371704
Method of erasing UPROM transistors Jan 11, 1995 Issued
Array ( [id] => 3441807 [patent_doc_number] => 05466613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Method of manufacturing a camera device' [patent_app_type] => 1 [patent_app_number] => 8/370958 [patent_app_country] => US [patent_app_date] => 1995-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5559 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/466/05466613.pdf [firstpage_image] =>[orig_patent_app_number] => 370958 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/370958
Method of manufacturing a camera device Jan 9, 1995 Issued
08/365743 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Dec 28, 1994 Abandoned
Array ( [id] => 3620404 [patent_doc_number] => 05641694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method of fabricating vertical epitaxial SOI transistor' [patent_app_type] => 1 [patent_app_number] => 8/361606 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 9016 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/641/05641694.pdf [firstpage_image] =>[orig_patent_app_number] => 361606 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361606
Method of fabricating vertical epitaxial SOI transistor Dec 21, 1994 Issued
Array ( [id] => 3649213 [patent_doc_number] => 05605845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Manufacture of electronic devices comprising thin-film transistors having self-aligned plural gates' [patent_app_type] => 1 [patent_app_number] => 8/359372 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4655 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/605/05605845.pdf [firstpage_image] =>[orig_patent_app_number] => 359372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359372
Manufacture of electronic devices comprising thin-film transistors having self-aligned plural gates Dec 19, 1994 Issued
Array ( [id] => 3524349 [patent_doc_number] => 05504017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Void detection in metallization patterns' [patent_app_type] => 1 [patent_app_number] => 8/359464 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2711 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504017.pdf [firstpage_image] =>[orig_patent_app_number] => 359464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359464
Void detection in metallization patterns Dec 19, 1994 Issued
Array ( [id] => 3686556 [patent_doc_number] => 05696003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Method for fabricating a semiconductor device using a catalyst introduction region' [patent_app_type] => 1 [patent_app_number] => 8/357648 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 108 [patent_no_of_words] => 28005 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696003.pdf [firstpage_image] =>[orig_patent_app_number] => 357648 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357648
Method for fabricating a semiconductor device using a catalyst introduction region Dec 15, 1994 Issued
Array ( [id] => 3554903 [patent_doc_number] => 05543361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Process for forming titanium silicide local interconnect' [patent_app_type] => 1 [patent_app_number] => 8/351843 [patent_app_country] => US [patent_app_date] => 1994-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 32 [patent_no_of_words] => 2817 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543361.pdf [firstpage_image] =>[orig_patent_app_number] => 351843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/351843
Process for forming titanium silicide local interconnect Dec 7, 1994 Issued
08/347530 PROCESS FOR FORMING GATE OXIDES POSSESSING DIFFERENT THICKNESSES ON A SEMICONDUCTOR SUBSTRATE Nov 29, 1994 Abandoned
Array ( [id] => 3588655 [patent_doc_number] => 05585291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method for manufacturing a semiconductor device containing a crystallization promoting material' [patent_app_type] => 1 [patent_app_number] => 8/350114 [patent_app_country] => US [patent_app_date] => 1994-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 28 [patent_no_of_words] => 10226 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585291.pdf [firstpage_image] =>[orig_patent_app_number] => 350114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/350114
Method for manufacturing a semiconductor device containing a crystallization promoting material Nov 28, 1994 Issued
08/345178 METHOD AND SYSTEM FOR PROVIDING AN INTEGRATED CIRCUIT DEVICE THAT ALLOWS FOR A HIGH FIELD THRESHOLD VOLTAGE UTILIZING OXIDE SPACERS Nov 27, 1994 Abandoned
Array ( [id] => 3589392 [patent_doc_number] => 05496768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method of manufacturing polycrystalline silicon thin film' [patent_app_type] => 1 [patent_app_number] => 8/344502 [patent_app_country] => US [patent_app_date] => 1994-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4806 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496768.pdf [firstpage_image] =>[orig_patent_app_number] => 344502 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/344502
Method of manufacturing polycrystalline silicon thin film Nov 22, 1994 Issued
08/342736 STRUCTURE FOR USE IN PRODUCING SEMICONDUCTOR DEVICES WITH BURIED CONTACTS AND METHOD FOR ITS PREPARATION Nov 20, 1994 Abandoned
Array ( [id] => 3519083 [patent_doc_number] => 05529951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Method of forming polycrystalline silicon layer on substrate by large area excimer laser irradiation' [patent_app_type] => 1 [patent_app_number] => 8/332758 [patent_app_country] => US [patent_app_date] => 1994-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 54 [patent_no_of_words] => 16642 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529951.pdf [firstpage_image] =>[orig_patent_app_number] => 332758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332758
Method of forming polycrystalline silicon layer on substrate by large area excimer laser irradiation Oct 31, 1994 Issued
Array ( [id] => 3526013 [patent_doc_number] => 05541137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Method of forming improved contacts from polysilicon to silicon or other polysilicon layers' [patent_app_type] => 1 [patent_app_number] => 8/330170 [patent_app_country] => US [patent_app_date] => 1994-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2478 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541137.pdf [firstpage_image] =>[orig_patent_app_number] => 330170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/330170
Method of forming improved contacts from polysilicon to silicon or other polysilicon layers Oct 26, 1994 Issued
Array ( [id] => 3687114 [patent_doc_number] => 05643826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/329644 [patent_app_country] => US [patent_app_date] => 1994-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 11008 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643826.pdf [firstpage_image] =>[orig_patent_app_number] => 329644 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/329644
Method for manufacturing a semiconductor device Oct 24, 1994 Issued
08/328096 THIN FILM TRANSISTORS AND METHOD OF FORMING THIN FILM TRANSISTORS Oct 23, 1994 Abandoned
Array ( [id] => 3546694 [patent_doc_number] => 05545572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method for fabricating electrostatic discharge protecting transistor' [patent_app_type] => 1 [patent_app_number] => 8/326880 [patent_app_country] => US [patent_app_date] => 1994-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2198 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/545/05545572.pdf [firstpage_image] =>[orig_patent_app_number] => 326880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/326880
Method for fabricating electrostatic discharge protecting transistor Oct 20, 1994 Issued
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