Leonard Chang

Array ( [id] => 111658 [patent_doc_number] => 07718494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach' [patent_app_type] => utility [patent_app_number] => 11/784721 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3475 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/718/07718494.pdf [firstpage_image] =>[orig_patent_app_number] => 11784721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4523246 [patent_doc_number] => 07951683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-31 [patent_title] => 'In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill' [patent_app_type] => utility [patent_app_number] => 11/697611 [patent_app_country] => US [patent_app_date] => 2007-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 10680 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/951/07951683.pdf [firstpage_image] =>[orig_patent_app_number] => 11697611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5126039 [patent_doc_number] => 20070238310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SILICON OXYNITRIDE FILM' [patent_app_type] => utility [patent_app_number] => 11/697082 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20070238310.pdf [firstpage_image] =>[orig_patent_app_number] => 11697082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4682400 [patent_doc_number] => 20080248626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY' [patent_app_type] => utility [patent_app_number] => 11/697102 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20080248626.pdf [firstpage_image] =>[orig_patent_app_number] => 11697102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4679898 [patent_doc_number] => 20080246124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'PLASMA TREATMENT OF INSULATING MATERIAL' [patent_app_type] => utility [patent_app_number] => 11/696262 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2943 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20080246124.pdf [firstpage_image] =>[orig_patent_app_number] => 11696262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4682384 [patent_doc_number] => 20080248610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'THERMAL BONDING PROCESS FOR CHIP PACKAGING' [patent_app_type] => utility [patent_app_number] => 11/695618 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20080248610.pdf [firstpage_image] =>[orig_patent_app_number] => 11695618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8340102 [patent_doc_number] => 08242028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-14 [patent_title] => 'UV treatment of etch stop and hard mask films for selectivity and hermeticity enhancement' [patent_app_type] => utility [patent_app_number] => 11/696102 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11696102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4506534 [patent_doc_number] => 07915055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/693776 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 11655 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915055.pdf [firstpage_image] =>[orig_patent_app_number] => 11693776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 62403 [patent_doc_number] => 07763317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'High K dielectric growth on metal triflate or trifluoroacetate terminated III-V semiconductor surfaces' [patent_app_type] => utility [patent_app_number] => 11/694781 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763317.pdf [firstpage_image] =>[orig_patent_app_number] => 11694781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4719595 [patent_doc_number] => 20080242118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHODS FOR FORMING DENSE DIELECTRIC LAYER OVER POROUS DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 11/693271 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3828 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242118.pdf [firstpage_image] =>[orig_patent_app_number] => 11693271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715204 [patent_doc_number] => 20080237726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'STRUCTURE AND METHODS FOR STRESS CONCENTRATING SPACER' [patent_app_type] => utility [patent_app_number] => 11/692371 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8883 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237726.pdf [firstpage_image] =>[orig_patent_app_number] => 11692371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7691966 [patent_doc_number] => 20070232067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Semiconductor Fabrication Method and Etching System' [patent_app_type] => utility [patent_app_number] => 11/692241 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12739 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232067.pdf [firstpage_image] =>[orig_patent_app_number] => 11692241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4890085 [patent_doc_number] => 20080099181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'METHOD TO COOL A BAKE PLATE USING AN ACTIVELY CHILLED TRANSFER SHUTTLE' [patent_app_type] => utility [patent_app_number] => 11/691461 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7316 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20080099181.pdf [firstpage_image] =>[orig_patent_app_number] => 11691461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4719480 [patent_doc_number] => 20080242003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'INTEGRATED CIRCUIT DEVICES WITH INTEGRAL HEAT SINKS' [patent_app_type] => utility [patent_app_number] => 11/691371 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3418 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242003.pdf [firstpage_image] =>[orig_patent_app_number] => 11691371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8486965 [patent_doc_number] => 20120286372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'Reliability of high-K gate dielectric layers' [patent_app_type] => utility [patent_app_number] => 11/725521 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4485 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11725521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4822098 [patent_doc_number] => 20080227254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'ELECTRONIC DEVICE INCLUDING CHANNEL REGIONS LYING AT DIFFERENT ELEVATIONS AND PROCESSES OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/685297 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20080227254.pdf [firstpage_image] =>[orig_patent_app_number] => 11685297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4933046 [patent_doc_number] => 20080003821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/716331 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003821.pdf [firstpage_image] =>[orig_patent_app_number] => 11716331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4696748 [patent_doc_number] => 20080218932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Embedded capacitor' [patent_app_type] => utility [patent_app_number] => 11/715651 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20080218932.pdf [firstpage_image] =>[orig_patent_app_number] => 11715651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 111682 [patent_doc_number] => 07718507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Bonded wafer and method of producing the same' [patent_app_type] => utility [patent_app_number] => 11/716341 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4493 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/718/07718507.pdf [firstpage_image] =>[orig_patent_app_number] => 11716341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5131201 [patent_doc_number] => 20070207598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Method for producing a substrate by germanium condensation' [patent_app_type] => utility [patent_app_number] => 11/707072 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3765 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20070207598.pdf [firstpage_image] =>[orig_patent_app_number] => 11707072 [rel_patent_id] =>[rel_patent_doc_number] =>)