Search

Leonard Chang

Supervisory Patent Examiner (ID: 9777, Phone: (571)270-3691 , Office: P/4166 )

Most Active Art Unit
2812
Art Unit(s)
2812, 4100, 2898, 4121
Total Applications
320
Issued Applications
197
Pending Applications
1
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5683025 [patent_doc_number] => 20060199295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Image sensor and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 11/369474 [patent_app_country] => US [patent_app_date] => 2006-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10243 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199295.pdf [firstpage_image] =>[orig_patent_app_number] => 11369474 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/369474
Image sensor and methods of forming the same Mar 6, 2006 Abandoned
Array ( [id] => 5700189 [patent_doc_number] => 20060216874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method for forming low temperature polysilicon thin film transistor with low doped drain structure' [patent_app_type] => utility [patent_app_number] => 11/368441 [patent_app_country] => US [patent_app_date] => 2006-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2010 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20060216874.pdf [firstpage_image] =>[orig_patent_app_number] => 11368441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/368441
Method for forming low temperature polysilicon thin film transistor with low doped drain structure Mar 6, 2006 Issued
Array ( [id] => 5682676 [patent_doc_number] => 20060198946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Method and apparatus for fabricating self-emission device' [patent_app_type] => utility [patent_app_number] => 11/366571 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7363 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20060198946.pdf [firstpage_image] =>[orig_patent_app_number] => 11366571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/366571
Method and apparatus for fabricating self-emission device Mar 2, 2006 Abandoned
Array ( [id] => 277904 [patent_doc_number] => 07556978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Piezoelectric MEMS switches and methods of making' [patent_app_type] => utility [patent_app_number] => 11/363791 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3077 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/556/07556978.pdf [firstpage_image] =>[orig_patent_app_number] => 11363791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363791
Piezoelectric MEMS switches and methods of making Feb 27, 2006 Issued
Array ( [id] => 5005084 [patent_doc_number] => 20070202654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS LINER' [patent_app_type] => utility [patent_app_number] => 11/307928 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2122 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20070202654.pdf [firstpage_image] =>[orig_patent_app_number] => 11307928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/307928
Spacer and process to enhance the strain in the channel with stress liner Feb 27, 2006 Issued
Array ( [id] => 278824 [patent_doc_number] => 07557904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Wafer holding mechanism' [patent_app_type] => utility [patent_app_number] => 11/360814 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6707 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557904.pdf [firstpage_image] =>[orig_patent_app_number] => 11360814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360814
Wafer holding mechanism Feb 23, 2006 Issued
Array ( [id] => 5230866 [patent_doc_number] => 20070292974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Substrate Processing Method and Substrate Processing Apparatus' [patent_app_type] => utility [patent_app_number] => 11/664282 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20070292974.pdf [firstpage_image] =>[orig_patent_app_number] => 11664282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/664282
Substrate Processing Method and Substrate Processing Apparatus Jan 26, 2006 Abandoned
Array ( [id] => 5869023 [patent_doc_number] => 20060163640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method of fabricating metal-insulator-metal capacitor and metal-insulator-metal capacitor manufactured by the method' [patent_app_type] => utility [patent_app_number] => 11/339151 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5166 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163640.pdf [firstpage_image] =>[orig_patent_app_number] => 11339151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339151
Method of fabricating metal-insulator-metal capacitor and metal-insulator-metal capacitor manufactured by the method Jan 24, 2006 Issued
Array ( [id] => 5642848 [patent_doc_number] => 20060281303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Tack & fuse chip bonding' [patent_app_type] => utility [patent_app_number] => 11/330011 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 123 [patent_figures_cnt] => 123 [patent_no_of_words] => 47784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20060281303.pdf [firstpage_image] =>[orig_patent_app_number] => 11330011 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/330011
Tack & fuse chip bonding Jan 9, 2006 Abandoned
Array ( [id] => 4483588 [patent_doc_number] => 07901994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Methods of manufacturing group III nitride semiconductor devices with silicon nitride layers' [patent_app_type] => utility [patent_app_number] => 11/286805 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11142 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/901/07901994.pdf [firstpage_image] =>[orig_patent_app_number] => 11286805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286805
Methods of manufacturing group III nitride semiconductor devices with silicon nitride layers Nov 22, 2005 Issued
Array ( [id] => 228799 [patent_doc_number] => 07601612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-13 [patent_title] => 'Method for forming solder joints for a flip chip assembly' [patent_app_type] => utility [patent_app_number] => 11/255971 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2689 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/601/07601612.pdf [firstpage_image] =>[orig_patent_app_number] => 11255971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255971
Method for forming solder joints for a flip chip assembly Oct 23, 2005 Issued
Array ( [id] => 5165682 [patent_doc_number] => 20070287269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method For Producing Semiconductor Wafer' [patent_app_type] => utility [patent_app_number] => 11/665362 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8622 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287269.pdf [firstpage_image] =>[orig_patent_app_number] => 11665362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/665362
Method For Producing Semiconductor Wafer Oct 13, 2005 Abandoned
Array ( [id] => 141853 [patent_doc_number] => 07691665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Process for making an organic field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/666751 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4014 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/691/07691665.pdf [firstpage_image] =>[orig_patent_app_number] => 11666751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/666751
Process for making an organic field effect transistor Oct 3, 2005 Issued
Array ( [id] => 4933151 [patent_doc_number] => 20080003926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Method of Grinding Multilayer Body and Method of Manufacturing Solid State Image Pickup Device' [patent_app_type] => utility [patent_app_number] => 11/663561 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003926.pdf [firstpage_image] =>[orig_patent_app_number] => 11663561 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/663561
Method of Grinding Multilayer Body and Method of Manufacturing Solid State Image Pickup Device Sep 26, 2005 Abandoned
Array ( [id] => 133764 [patent_doc_number] => 07696533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Indium nitride layer production' [patent_app_type] => utility [patent_app_number] => 11/662491 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3503 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696533.pdf [firstpage_image] =>[orig_patent_app_number] => 11662491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/662491
Indium nitride layer production Sep 13, 2005 Issued
Array ( [id] => 5165615 [patent_doc_number] => 20070287202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method for Producing Nano-Scale Low-Dimensional Quantum Structure, and Method for Producing Integrated Circuit Using the Method for Producing the Structure' [patent_app_type] => utility [patent_app_number] => 11/660931 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287202.pdf [firstpage_image] =>[orig_patent_app_number] => 11660931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/660931
Method for Producing Nano-Scale Low-Dimensional Quantum Structure, and Method for Producing Integrated Circuit Using the Method for Producing the Structure Aug 29, 2005 Abandoned
Array ( [id] => 5259205 [patent_doc_number] => 20070212837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Method And Apparatus Of Fabricating Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/596372 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5559 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20070212837.pdf [firstpage_image] =>[orig_patent_app_number] => 11596372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/596372
Method and apparatus of fabricating semiconductor device May 11, 2005 Issued
Array ( [id] => 5800627 [patent_doc_number] => 20060035439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Method of forming a micromechanical structure' [patent_app_type] => utility [patent_app_number] => 10/917362 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4499 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20060035439.pdf [firstpage_image] =>[orig_patent_app_number] => 10917362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917362
Method of foming a micromechanical structure Aug 12, 2004 Issued
10/761098 LEAD FRAME, RESIN-MOLDED SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME, Jan 20, 2004 Abandoned
Menu