Search

Leonard Chang

Supervisory Patent Examiner (ID: 7771, Phone: (571)270-3691 , Office: P/4166 )

Most Active Art Unit
2812
Art Unit(s)
4121, 4100, 2812, 2898
Total Applications
320
Issued Applications
197
Pending Applications
1
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8446210 [patent_doc_number] => 08288261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-16 [patent_title] => 'Method for preparing contact plug structure' [patent_app_type] => utility [patent_app_number] => 13/093008 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2309 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093008
Method for preparing contact plug structure Apr 24, 2011 Issued
Array ( [id] => 9762175 [patent_doc_number] => 08846496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Manufacturing method of single crystal semiconductor film and manufacturing method of electrode' [patent_app_type] => utility [patent_app_number] => 13/092249 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4614 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092249
Manufacturing method of single crystal semiconductor film and manufacturing method of electrode Apr 21, 2011 Issued
Array ( [id] => 7486186 [patent_doc_number] => 20110250748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/076660 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8244 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250748.pdf [firstpage_image] =>[orig_patent_app_number] => 13076660 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/076660
Method of manufacturing semiconductor device Mar 30, 2011 Issued
Array ( [id] => 8690577 [patent_doc_number] => 08390106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Circuit board with built-in semiconductor chip and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/076525 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 15935 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13076525 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/076525
Circuit board with built-in semiconductor chip and method of manufacturing the same Mar 30, 2011 Issued
Array ( [id] => 8064747 [patent_doc_number] => 20110244649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/075624 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2743 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20110244649.pdf [firstpage_image] =>[orig_patent_app_number] => 13075624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075624
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Mar 29, 2011 Abandoned
Array ( [id] => 8430340 [patent_doc_number] => 20120252216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'Low-Temperature in-situ Removal of Oxide from a Silicon Surface During CMOS Epitaxial Processing' [patent_app_type] => utility [patent_app_number] => 13/075657 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2292 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13075657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075657
Low-temperature in-situ removal of oxide from a silicon surface during CMOS epitaxial processing Mar 29, 2011 Issued
Array ( [id] => 8430335 [patent_doc_number] => 20120252210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHOD FOR MODIFYING METAL CAP LAYERS IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/076016 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13076016 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/076016
METHOD FOR MODIFYING METAL CAP LAYERS IN SEMICONDUCTOR DEVICES Mar 29, 2011 Abandoned
Array ( [id] => 8629822 [patent_doc_number] => 08361893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Semiconductor device and substrate with chalcogen doped region' [patent_app_type] => utility [patent_app_number] => 13/075475 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6850 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13075475 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075475
Semiconductor device and substrate with chalcogen doped region Mar 29, 2011 Issued
Array ( [id] => 8064707 [patent_doc_number] => 20110244665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'MANUFACTURING METHOD OF GaN BASED SEMICONDUCTOR EPITAXIAL SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/075659 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4130 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20110244665.pdf [firstpage_image] =>[orig_patent_app_number] => 13075659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075659
MANUFACTURING METHOD OF GaN BASED SEMICONDUCTOR EPITAXIAL SUBSTRATE Mar 29, 2011 Abandoned
Array ( [id] => 8591836 [patent_doc_number] => 08349712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Layer assembly' [patent_app_type] => utility [patent_app_number] => 13/076166 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2876 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13076166 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/076166
Layer assembly Mar 29, 2011 Issued
Array ( [id] => 7656930 [patent_doc_number] => 20110306199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/075658 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20110306199.pdf [firstpage_image] =>[orig_patent_app_number] => 13075658 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075658
Method for manufacturing nonvolatile memory device Mar 29, 2011 Issued
Array ( [id] => 8725468 [patent_doc_number] => 08404583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Conformality of oxide layers along sidewalls of deep vias' [patent_app_type] => utility [patent_app_number] => 13/035034 [patent_app_country] => US [patent_app_date] => 2011-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3791 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13035034 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/035034
Conformality of oxide layers along sidewalls of deep vias Feb 24, 2011 Issued
Array ( [id] => 8435487 [patent_doc_number] => 08283256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Methods of forming microdevice substrates using double-sided alignment techniques' [patent_app_type] => utility [patent_app_number] => 13/034004 [patent_app_country] => US [patent_app_date] => 2011-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2506 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13034004 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/034004
Methods of forming microdevice substrates using double-sided alignment techniques Feb 23, 2011 Issued
Array ( [id] => 7767169 [patent_doc_number] => 20120034716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 13/034619 [patent_app_country] => US [patent_app_date] => 2011-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2049 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034716.pdf [firstpage_image] =>[orig_patent_app_number] => 13034619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/034619
METHOD FOR MANUFACTURING LIGHT EMITTING DIODE Feb 23, 2011 Abandoned
Array ( [id] => 6213005 [patent_doc_number] => 20110136305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'Group III Nitride Semiconductor Devices with Silicon Nitride Layers and Methods of Manufacturing Such Devices' [patent_app_type] => utility [patent_app_number] => 13/010053 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11183 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20110136305.pdf [firstpage_image] =>[orig_patent_app_number] => 13010053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/010053
Group III nitride semiconductor devices with silicon nitride layers and methods of manufacturing such devices Jan 19, 2011 Issued
Array ( [id] => 5944252 [patent_doc_number] => 20110104872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Method of manufacturing a semiconductor device having a heat spreader' [patent_app_type] => utility [patent_app_number] => 12/929291 [patent_app_country] => US [patent_app_date] => 2011-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5793 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20110104872.pdf [firstpage_image] =>[orig_patent_app_number] => 12929291 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929291
Method of manufacturing a semiconductor device having a heat spreader Jan 11, 2011 Abandoned
Array ( [id] => 8621417 [patent_doc_number] => 08354330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Method of fabricating SOI super-junction LDMOS structure capable of completely eliminating substrate-assisted depletion effects' [patent_app_type] => utility [patent_app_number] => 13/203724 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2137 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13203724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/203724
Method of fabricating SOI super-junction LDMOS structure capable of completely eliminating substrate-assisted depletion effects Dec 14, 2010 Issued
Array ( [id] => 8237452 [patent_doc_number] => 20120146187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'METHODS AND STRUCTURES FOR INCREASED THERMAL DISSIPATION OF THIN FILM RESISTORS' [patent_app_type] => utility [patent_app_number] => 12/968001 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12968001 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/968001
Methods and structures for increased thermal dissipation of thin film resistors Dec 13, 2010 Issued
Array ( [id] => 8340045 [patent_doc_number] => 08241968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Printed circuit board (PCB) including a wire pattern, semiconductor package including the PCB, electrical and electronic apparatus including the semiconductor package, method of fabricating the PCB, and method of fabricating the semiconductor package' [patent_app_type] => utility [patent_app_number] => 12/938534 [patent_app_country] => US [patent_app_date] => 2010-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 7328 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12938534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938534
Printed circuit board (PCB) including a wire pattern, semiconductor package including the PCB, electrical and electronic apparatus including the semiconductor package, method of fabricating the PCB, and method of fabricating the semiconductor package Nov 2, 2010 Issued
Array ( [id] => 7818039 [patent_doc_number] => 20120064659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD FOR MANUFACTURING SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 12/938857 [patent_app_country] => US [patent_app_date] => 2010-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3073 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064659.pdf [firstpage_image] =>[orig_patent_app_number] => 12938857 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938857
METHOD FOR MANUFACTURING SOLAR CELL Nov 2, 2010 Abandoned
Menu