
Lesley D. Morris
Examiner (ID: 8752)
| Most Active Art Unit | 3104 |
| Art Unit(s) | 4100, 3104, 3611, 3727, 3752, 2899 |
| Total Applications | 1257 |
| Issued Applications | 1024 |
| Pending Applications | 149 |
| Abandoned Applications | 84 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5743276
[patent_doc_number] => 20060089001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Localized use of high-K dielectric for high performance capacitor structures'
[patent_app_type] => utility
[patent_app_number] => 10/974115
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2125
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20060089001.pdf
[firstpage_image] =>[orig_patent_app_number] => 10974115
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/974115 | Localized use of high-K dielectric for high performance capacitor structures | Oct 26, 2004 | Abandoned |
Array
(
[id] => 7139969
[patent_doc_number] => 20050116214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Back-gated field emission electron source'
[patent_app_type] => utility
[patent_app_number] => 10/974895
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9100
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0116/20050116214.pdf
[firstpage_image] =>[orig_patent_app_number] => 10974895
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/974895 | Back-gated field emission electron source | Oct 26, 2004 | Abandoned |
Array
(
[id] => 5817980
[patent_doc_number] => 20060022293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'Economical and very simple to fabricate single device equivalent to CMOS, and other semiconductor devices in compensated semiconductor'
[patent_app_type] => utility
[patent_app_number] => 10/967774
[patent_app_country] => US
[patent_app_date] => 2004-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 21819
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20060022293.pdf
[firstpage_image] =>[orig_patent_app_number] => 10967774
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/967774 | Economical and very simple to fabricate single device equivalent to CMOS, and other semiconductor devices in compensated semiconductor | Oct 17, 2004 | Abandoned |
Array
(
[id] => 7220529
[patent_doc_number] => 20050077600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/952796
[patent_app_country] => US
[patent_app_date] => 2004-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7832
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077600.pdf
[firstpage_image] =>[orig_patent_app_number] => 10952796
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/952796 | Semiconductor device | Sep 29, 2004 | Abandoned |
Array
(
[id] => 5634989
[patent_doc_number] => 20060065962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Control circuitry in stacked silicon'
[patent_app_type] => utility
[patent_app_number] => 10/954256
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4382
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20060065962.pdf
[firstpage_image] =>[orig_patent_app_number] => 10954256
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/954256 | Control circuitry in stacked silicon | Sep 28, 2004 | Abandoned |
Array
(
[id] => 256711
[patent_doc_number] => 07576388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-08-18
[patent_title] => 'Trench-gate LDMOS structures'
[patent_app_type] => utility
[patent_app_number] => 10/951259
[patent_app_country] => US
[patent_app_date] => 2004-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 7955
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/576/07576388.pdf
[firstpage_image] =>[orig_patent_app_number] => 10951259
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/951259 | Trench-gate LDMOS structures | Sep 25, 2004 | Issued |
Array
(
[id] => 75209
[patent_doc_number] => 07750402
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-06
[patent_title] => 'Lateral planar type power semiconductor device including drain buried region immediately below drain region and its manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 10/925035
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 5563
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/750/07750402.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925035
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925035 | Lateral planar type power semiconductor device including drain buried region immediately below drain region and its manufacturing method | Aug 24, 2004 | Issued |
Array
(
[id] => 8270249
[patent_doc_number] => 08211753
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'Leadframe-based mold array package heat spreader and fabrication method therefor'
[patent_app_type] => utility
[patent_app_number] => 10/921376
[patent_app_country] => US
[patent_app_date] => 2004-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 5624
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10921376
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/921376 | Leadframe-based mold array package heat spreader and fabrication method therefor | Aug 17, 2004 | Issued |
Array
(
[id] => 7086665
[patent_doc_number] => 20050006777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 10/912216
[patent_app_country] => US
[patent_app_date] => 2004-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2174
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20050006777.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912216
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912216 | Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof | Aug 5, 2004 | Abandoned |
Array
(
[id] => 5770964
[patent_doc_number] => 20050266601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => '[PHOTOELECTRIC DEVICE GRINDING PROCESS AND DEVICE GRINDING PROCESS]'
[patent_app_type] => utility
[patent_app_number] => 10/710696
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2400
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20050266601.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710696
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710696 | Photoelectric device grinding process and device grinding process | Jul 28, 2004 | Issued |
Array
(
[id] => 7089145
[patent_doc_number] => 20050009258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/901124
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3028
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20050009258.pdf
[firstpage_image] =>[orig_patent_app_number] => 10901124
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901124 | Semiconductor device having a memory cell section, an adjacent circuit section, and silicide formed on an impurity diffused region | Jul 28, 2004 | Issued |
Array
(
[id] => 7328983
[patent_doc_number] => 20040253810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-16
[patent_title] => 'Dummy structures to reduce metal recess in electropolishing process'
[patent_app_type] => new
[patent_app_number] => 10/487565
[patent_app_country] => US
[patent_app_date] => 2004-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 7280
[patent_no_of_claims] => 91
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20040253810.pdf
[firstpage_image] =>[orig_patent_app_number] => 10487565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/487565 | Dummy structures to reduce metal recess in electropolishing process | Jul 26, 2004 | Abandoned |
Array
(
[id] => 5763175
[patent_doc_number] => 20060017114
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'METHOD FOR FABRICATING INTEGRATED CIRCUITS HAVING BOTH HIGH VOLTAGE AND LOW VOLTAGE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 10/710616
[patent_app_country] => US
[patent_app_date] => 2004-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 3515
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20060017114.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710616
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710616 | Method for fabricating integrated circuits having both high voltage and low voltage devices | Jul 24, 2004 | Issued |
Array
(
[id] => 7338502
[patent_doc_number] => 20040245580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => '[CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME]'
[patent_app_type] => new
[patent_app_number] => 10/710596
[patent_app_country] => US
[patent_app_date] => 2004-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4348
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20040245580.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710596 | Chip structure with a passive device and method for forming the same | Jul 22, 2004 | Issued |
Array
(
[id] => 7242200
[patent_doc_number] => 20050073061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Static random access memories including a silicon-on-insulator substrate'
[patent_app_type] => utility
[patent_app_number] => 10/893815
[patent_app_country] => US
[patent_app_date] => 2004-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7285
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073061.pdf
[firstpage_image] =>[orig_patent_app_number] => 10893815
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/893815 | Static random access memories including a silicon-on-insulator substrate | Jul 18, 2004 | Issued |
Array
(
[id] => 5790890
[patent_doc_number] => 20060011966
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Structure of a non-volatile memory cell and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 10/891076
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3313
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20060011966.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891076
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891076 | Structure of a non-volatile memory cell and method of forming the same | Jul 14, 2004 | Issued |
Array
(
[id] => 4610460
[patent_doc_number] => 07994611
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-08-09
[patent_title] => 'Bipolar transistor fabricated in a biCMOS process'
[patent_app_type] => utility
[patent_app_number] => 10/892015
[patent_app_country] => US
[patent_app_date] => 2004-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3866
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/994/07994611.pdf
[firstpage_image] =>[orig_patent_app_number] => 10892015
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892015 | Bipolar transistor fabricated in a biCMOS process | Jul 13, 2004 | Issued |
Array
(
[id] => 8543926
[patent_doc_number] => 08319219
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-27
[patent_title] => 'Light-emitting device'
[patent_app_type] => utility
[patent_app_number] => 10/885651
[patent_app_country] => US
[patent_app_date] => 2004-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 40
[patent_no_of_words] => 13187
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10885651
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/885651 | Light-emitting device | Jul 7, 2004 | Issued |
Array
(
[id] => 142590
[patent_doc_number] => 07687827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'III-nitride materials including low dislocation densities and methods associated with the same'
[patent_app_type] => utility
[patent_app_number] => 10/886506
[patent_app_country] => US
[patent_app_date] => 2004-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 10902
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/687/07687827.pdf
[firstpage_image] =>[orig_patent_app_number] => 10886506
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/886506 | III-nitride materials including low dislocation densities and methods associated with the same | Jul 6, 2004 | Issued |
Array
(
[id] => 7022961
[patent_doc_number] => 20050017355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'Water level processing method and structure to manufacture two kinds of bumps, gold and solder, on one wafer'
[patent_app_type] => utility
[patent_app_number] => 10/855086
[patent_app_country] => US
[patent_app_date] => 2004-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3954
[patent_no_of_claims] => 203
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20050017355.pdf
[firstpage_image] =>[orig_patent_app_number] => 10855086
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/855086 | Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer | May 26, 2004 | Issued |