Search

Leslie C. Pascal

Examiner (ID: 18581)

Most Active Art Unit
2613
Art Unit(s)
2874, 2616, 2613, 2637, 2612, 2607, 2733, 2883, 2603, 2636, 2608, 2606, 2633
Total Applications
2250
Issued Applications
1890
Pending Applications
78
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16180934 [patent_doc_number] => 20200227903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Charging Box Unit for a Charging Station [patent_app_type] => utility [patent_app_number] => 16/628866 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16628866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/628866
Charging Box Unit for a Charging Station Jun 24, 2018 Abandoned
Array ( [id] => 15297941 [patent_doc_number] => 20190392106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => OPTIMIZING LIBRARY CELLS WITH WIRING IN METALLIZATION LAYERS [patent_app_type] => utility [patent_app_number] => 16/014287 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014287
Optimizing library cells with wiring in metallization layers Jun 20, 2018 Issued
Array ( [id] => 15297935 [patent_doc_number] => 20190392103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => Error Detection Technique Based on Identifying Data Trend Issues [patent_app_type] => utility [patent_app_number] => 16/013937 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013937
Error detection technique based on identifying data trend issues Jun 20, 2018 Issued
Array ( [id] => 15297949 [patent_doc_number] => 20190392110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => MODIFYING LAYOUT BY REMOVING FILL CELL FROM FILL-DENSE REGIONS AND INSERTING DUPLICATE IN TARGET FILL REGION [patent_app_type] => utility [patent_app_number] => 16/013403 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013403 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013403
Modifying layout by removing fill cell from fill-dense regions and inserting duplicate in target fill region Jun 19, 2018 Issued
Array ( [id] => 16291384 [patent_doc_number] => 10768227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device [patent_app_type] => utility [patent_app_number] => 16/013931 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3680 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013931 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013931
Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device Jun 19, 2018 Issued
Array ( [id] => 13797771 [patent_doc_number] => 20190012424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => SYSTEM AND METHOD FOR ELECTRONIC AUTOMATED PRINTED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 16/011837 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011837
System and method for electronic automated printed circuit design Jun 18, 2018 Issued
Array ( [id] => 16088973 [patent_doc_number] => 20200198473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD FOR DETECTING A PLUG-IN OPERATION [patent_app_type] => utility [patent_app_number] => 16/622835 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/622835
Method for detecting a plug-in operation Jun 7, 2018 Issued
Array ( [id] => 13615243 [patent_doc_number] => 20180359173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/000936 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/000936
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM Jun 5, 2018 Abandoned
Array ( [id] => 17540550 [patent_doc_number] => 11305658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Charger for charging an electric vehicle [patent_app_type] => utility [patent_app_number] => 16/617897 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 14737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16617897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/617897
Charger for charging an electric vehicle May 31, 2018 Issued
Array ( [id] => 15215497 [patent_doc_number] => 20190370435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => GENERATING SYNTHETIC LAYOUT PATTERNS BY FEEDFORWARD NEURAL NETWORK BASED VARIATIONAL AUTOENCODERS [patent_app_type] => utility [patent_app_number] => 15/994461 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994461
Generating synthetic layout patterns by feedforward neural network based variational autoencoders May 30, 2018 Issued
Array ( [id] => 15215495 [patent_doc_number] => 20190370434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => AUTOMATIC GENERATION OF VIA PATTERNS WITH COORDINATE-BASED RECURRENT NEURAL NETWORK (RNN) [patent_app_type] => utility [patent_app_number] => 15/994396 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994396
Automatic generation of via patterns with coordinate-based recurrent neural network (RNN) May 30, 2018 Issued
Array ( [id] => 15215493 [patent_doc_number] => 20190370433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Method of Redistribution Layer Routing for 2.5-Dimensional Integrated Circuit Packages [patent_app_type] => utility [patent_app_number] => 15/993606 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993606
Method of redistribution layer routing for 2.5-dimensional integrated circuit packages May 30, 2018 Issued
Array ( [id] => 15215489 [patent_doc_number] => 20190370431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => COORDINATES-BASED GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING SYNTHETIC PHYSICAL DESIGN LAYOUT PATTERNS [patent_app_type] => utility [patent_app_number] => 15/994598 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994598 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994598
Coordinates-based generative adversarial networks for generating synthetic physical design layout patterns May 30, 2018 Issued
Array ( [id] => 13595971 [patent_doc_number] => 20180349534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => OPTIMUM STAGE NUMBER CALCULATION METHOD, INFORMATION PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 15/992334 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/992334
Optimum stage number calculation method, information processing apparatus, and recording medium May 29, 2018 Issued
Array ( [id] => 13569513 [patent_doc_number] => 20180336304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => METHOD FOR COMPRESSION OF EMULATION TIME LINE IN PRESENCE OF DYNAMIC RE-PROGRAMMING OF CLOCKS [patent_app_type] => utility [patent_app_number] => 15/982997 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982997
Method for compression of emulation time line in presence of dynamic re-programming of clocks May 16, 2018 Issued
Array ( [id] => 15578741 [patent_doc_number] => 10579757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Calculating and extracting joule-heating and self-heat induced temperature on wire segments for chip reliability [patent_app_type] => utility [patent_app_number] => 15/979583 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 6074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979583
Calculating and extracting joule-heating and self-heat induced temperature on wire segments for chip reliability May 14, 2018 Issued
Array ( [id] => 16144703 [patent_doc_number] => 10705420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Mask bias approximation [patent_app_type] => utility [patent_app_number] => 15/979751 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979751
Mask bias approximation May 14, 2018 Issued
Array ( [id] => 15373941 [patent_doc_number] => 10528691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Method and system for automated selection of a subset of plurality of validation tests [patent_app_type] => utility [patent_app_number] => 15/978527 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978527
Method and system for automated selection of a subset of plurality of validation tests May 13, 2018 Issued
Array ( [id] => 16146255 [patent_doc_number] => 10706199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Graphical user interface for interactive macro-cell placement [patent_app_type] => utility [patent_app_number] => 15/979171 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979171
Graphical user interface for interactive macro-cell placement May 13, 2018 Issued
Array ( [id] => 13417931 [patent_doc_number] => 20180260508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => Method And Apparatus For Modeling Delays In Emulation [patent_app_type] => utility [patent_app_number] => 15/979194 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979194
Method and apparatus for modeling delays in emulation May 13, 2018 Issued
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