
Leslie J. Evanisko
Examiner (ID: 9151, Phone: (571)272-2161 , Office: P/2854 )
| Most Active Art Unit | 2853 |
| Art Unit(s) | 3307, 2853, 2854 |
| Total Applications | 1842 |
| Issued Applications | 1427 |
| Pending Applications | 72 |
| Abandoned Applications | 364 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9540100
[patent_doc_number] => 20140164747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'Branch-Free Condition Evaluation'
[patent_app_type] => utility
[patent_app_number] => 14/081480
[patent_app_country] => US
[patent_app_date] => 2013-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 13272
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081480
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081480 | Instructions and functions for evaluating program defined conditions | Nov 14, 2013 | Issued |
Array
(
[id] => 10015149
[patent_doc_number] => 09058163
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-16
[patent_title] => 'Known good code for on-chip device management'
[patent_app_type] => utility
[patent_app_number] => 14/079185
[patent_app_country] => US
[patent_app_date] => 2013-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6985
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079185
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/079185 | Known good code for on-chip device management | Nov 12, 2013 | Issued |
Array
(
[id] => 9320826
[patent_doc_number] => 20140053164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'Region-Weighted Accounting of Multi-Threaded Processor Core According to Dispatch State'
[patent_app_type] => utility
[patent_app_number] => 14/065617
[patent_app_country] => US
[patent_app_date] => 2013-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8269
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14065617
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/065617 | Region-weighted accounting of multi-threaded processor core according to dispatch state | Oct 28, 2013 | Issued |
Array
(
[id] => 9424092
[patent_doc_number] => 20140108743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-17
[patent_title] => 'STORE DATA FORWARDING WITH NO MEMORY MODEL RESTRICTIONS'
[patent_app_type] => utility
[patent_app_number] => 14/059673
[patent_app_country] => US
[patent_app_date] => 2013-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7755
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059673
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/059673 | Store data forwarding with no memory model restrictions | Oct 21, 2013 | Issued |
Array
(
[id] => 10131117
[patent_doc_number] => 09164952
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-20
[patent_title] => 'Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements'
[patent_app_type] => utility
[patent_app_number] => 14/035067
[patent_app_country] => US
[patent_app_date] => 2013-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 8325
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14035067
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/035067 | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements | Sep 23, 2013 | Issued |
Array
(
[id] => 10524388
[patent_doc_number] => 09250901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Execution context swap between heterogeneous functional hardware units'
[patent_app_type] => utility
[patent_app_number] => 13/795338
[patent_app_country] => US
[patent_app_date] => 2013-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 13749
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795338
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/795338 | Execution context swap between heterogeneous functional hardware units | Mar 11, 2013 | Issued |
Array
(
[id] => 10609833
[patent_doc_number] => 09329863
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-03
[patent_title] => 'Load register on condition with zero or immediate instruction'
[patent_app_type] => utility
[patent_app_number] => 13/793223
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7047
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793223
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/793223 | Load register on condition with zero or immediate instruction | Mar 10, 2013 | Issued |
Array
(
[id] => 11220467
[patent_doc_number] => 09448803
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-20
[patent_title] => 'System and method for hardware scheduling of conditional barriers and impatient barriers'
[patent_app_type] => utility
[patent_app_number] => 13/794578
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14463
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13794578
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/794578 | System and method for hardware scheduling of conditional barriers and impatient barriers | Mar 10, 2013 | Issued |
Array
(
[id] => 10637377
[patent_doc_number] => 09354880
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-31
[patent_title] => 'Processing device for high-speed execution of an xRISC computer program'
[patent_app_type] => utility
[patent_app_number] => 13/792489
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 7466
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792489
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792489 | Processing device for high-speed execution of an xRISC computer program | Mar 10, 2013 | Issued |
Array
(
[id] => 9036240
[patent_doc_number] => 20130238878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-12
[patent_title] => 'LOW POWER, HIGH PERFORMANCE, HETEROGENEOUS, SCALABLE PROCESSOR ARCHITECTURE'
[patent_app_type] => utility
[patent_app_number] => 13/775402
[patent_app_country] => US
[patent_app_date] => 2013-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 13632
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775402
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/775402 | Low power, high performance, heterogeneous, scalable processor architecture | Feb 24, 2013 | Issued |
Array
(
[id] => 11795710
[patent_doc_number] => 09405534
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-02
[patent_title] => 'Compound complex instruction set computer (CCISC) processor architecture'
[patent_app_type] => utility
[patent_app_number] => 13/746239
[patent_app_country] => US
[patent_app_date] => 2013-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 6839
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746239
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/746239 | Compound complex instruction set computer (CCISC) processor architecture | Jan 20, 2013 | Issued |
Array
(
[id] => 11801318
[patent_doc_number] => 09542193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-10
[patent_title] => 'Memory address collision detection of ordered parallel threads with bloom filters'
[patent_app_type] => utility
[patent_app_number] => 13/730704
[patent_app_country] => US
[patent_app_date] => 2012-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 5036
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730704
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/730704 | Memory address collision detection of ordered parallel threads with bloom filters | Dec 27, 2012 | Issued |
Array
(
[id] => 11584730
[patent_doc_number] => 09639372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-02
[patent_title] => 'Apparatus and method for heterogeneous processors mapping to virtual cores'
[patent_app_type] => utility
[patent_app_number] => 13/730565
[patent_app_country] => US
[patent_app_date] => 2012-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 28
[patent_no_of_words] => 20050
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730565
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/730565 | Apparatus and method for heterogeneous processors mapping to virtual cores | Dec 27, 2012 | Issued |
Array
(
[id] => 13172051
[patent_doc_number] => 10102142
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-16
[patent_title] => Virtual address based memory reordering
[patent_app_type] => utility
[patent_app_number] => 13/727457
[patent_app_country] => US
[patent_app_date] => 2012-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2940
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727457
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/727457 | Virtual address based memory reordering | Dec 25, 2012 | Issued |
Array
(
[id] => 11333078
[patent_doc_number] => 09524324
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-12-20
[patent_title] => 'Framework for performing updates of globally shared data in a multiprocessor environment'
[patent_app_type] => utility
[patent_app_number] => 13/726805
[patent_app_country] => US
[patent_app_date] => 2012-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 16340
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726805
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/726805 | Framework for performing updates of globally shared data in a multiprocessor environment | Dec 25, 2012 | Issued |
Array
(
[id] => 9563767
[patent_doc_number] => 20140181480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-26
[patent_title] => 'NESTED SPECULATIVE REGIONS FOR A SYNCHRONIZATION FACILITY'
[patent_app_type] => utility
[patent_app_number] => 13/723296
[patent_app_country] => US
[patent_app_date] => 2012-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6598
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723296
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/723296 | Nested speculative regions for a synchronization facility | Dec 20, 2012 | Issued |
Array
(
[id] => 9465385
[patent_doc_number] => 20140129812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'SYSTEM AND METHOD FOR EXECUTING SEQUENTIAL CODE USING A GROUP OF HREADS AND SINGLE-INSTRUCTION, MULTIPLE-THREAD PROCESSOR INCORPORATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/723981
[patent_app_country] => US
[patent_app_date] => 2012-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2627
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723981
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/723981 | System and method for executing sequential code using a group of threads and single-instruction, multiple-thread processor incorporating the same | Dec 20, 2012 | Issued |
Array
(
[id] => 9540093
[patent_doc_number] => 20140164740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'Branch-Free Condition Evaluation'
[patent_app_type] => utility
[patent_app_number] => 13/710826
[patent_app_country] => US
[patent_app_date] => 2012-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 13269
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13710826
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/710826 | Branch-free condition evaluation | Dec 10, 2012 | Issued |
Array
(
[id] => 11738985
[patent_doc_number] => 09703567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-11
[patent_title] => 'Control transfer termination instructions of an instruction set architecture (ISA)'
[patent_app_type] => utility
[patent_app_number] => 13/690221
[patent_app_country] => US
[patent_app_date] => 2012-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9621
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690221
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/690221 | Control transfer termination instructions of an instruction set architecture (ISA) | Nov 29, 2012 | Issued |
Array
(
[id] => 8722597
[patent_doc_number] => 20130073814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'Computer System'
[patent_app_type] => utility
[patent_app_number] => 13/675713
[patent_app_country] => US
[patent_app_date] => 2012-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4100
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675713
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/675713 | Computer System | Nov 12, 2012 | Abandoned |