
Leslie Pilar Cruz
Examiner (ID: 105, Phone: (571)272-8599 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 538 |
| Issued Applications | 372 |
| Pending Applications | 2 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5329728
[patent_doc_number] => 20090110205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'Portable Sound System Testing Apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/927098
[patent_app_country] => US
[patent_app_date] => 2007-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2931
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20090110205.pdf
[firstpage_image] =>[orig_patent_app_number] => 11927098
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/927098 | Portable Sound System Testing Apparatus | Oct 28, 2007 | Abandoned |
Array
(
[id] => 4669903
[patent_doc_number] => 20080044963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'TFT SUBSTRATE FOR LIQUID CRYSTAL DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/923822
[patent_app_country] => US
[patent_app_date] => 2007-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 11693
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20080044963.pdf
[firstpage_image] =>[orig_patent_app_number] => 11923822
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/923822 | TFT SUBSTRATE FOR LIQUID CRYSTAL DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME | Oct 24, 2007 | Abandoned |
Array
(
[id] => 4913117
[patent_doc_number] => 20080093716
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/874223
[patent_app_country] => US
[patent_app_date] => 2007-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3716
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20080093716.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874223
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Oct 17, 2007 | Abandoned |
Array
(
[id] => 4667142
[patent_doc_number] => 20080042202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS'
[patent_app_type] => utility
[patent_app_number] => 11/874753
[patent_app_country] => US
[patent_app_date] => 2007-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4441
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20080042202.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874753
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874753 | QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS | Oct 17, 2007 | Abandoned |
Array
(
[id] => 4488785
[patent_doc_number] => 07884384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-08
[patent_title] => 'Light emitting diode device and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/874834
[patent_app_country] => US
[patent_app_date] => 2007-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3979
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/884/07884384.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874834
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874834 | Light emitting diode device and fabrication method thereof | Oct 17, 2007 | Issued |
Array
(
[id] => 5582848
[patent_doc_number] => 20090102050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/873603
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20090102050.pdf
[firstpage_image] =>[orig_patent_app_number] => 11873603
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873603 | SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE | Oct 16, 2007 | Abandoned |
Array
(
[id] => 5582858
[patent_doc_number] => 20090102060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'Wafer Level Stacked Die Packaging'
[patent_app_type] => utility
[patent_app_number] => 11/874083
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2276
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20090102060.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874083
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874083 | Wafer level stacked die packaging | Oct 16, 2007 | Issued |
Array
(
[id] => 5582813
[patent_doc_number] => 20090102015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'Integrated Circuit, Memory Cell Array, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing an Integrated Circuit'
[patent_app_type] => utility
[patent_app_number] => 11/874113
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7195
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20090102015.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874113
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874113 | Integrated Circuit, Memory Cell Array, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing an Integrated Circuit | Oct 16, 2007 | Abandoned |
Array
(
[id] => 82811
[patent_doc_number] => 07745879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-29
[patent_title] => 'Method of fabricating high voltage fully depleted SOI transistor and structure thereof'
[patent_app_type] => utility
[patent_app_number] => 11/872953
[patent_app_country] => US
[patent_app_date] => 2007-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1628
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/745/07745879.pdf
[firstpage_image] =>[orig_patent_app_number] => 11872953
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/872953 | Method of fabricating high voltage fully depleted SOI transistor and structure thereof | Oct 15, 2007 | Issued |
Array
(
[id] => 4743342
[patent_doc_number] => 20080087943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/873104
[patent_app_country] => US
[patent_app_date] => 2007-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6953
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20080087943.pdf
[firstpage_image] =>[orig_patent_app_number] => 11873104
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873104 | Nonvolatile semiconductor memory device and method of fabricating the same | Oct 15, 2007 | Issued |
Array
(
[id] => 4883945
[patent_doc_number] => 20080258277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-23
[patent_title] => 'Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same'
[patent_app_type] => utility
[patent_app_number] => 11/866034
[patent_app_country] => US
[patent_app_date] => 2007-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5054
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0258/20080258277.pdf
[firstpage_image] =>[orig_patent_app_number] => 11866034
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/866034 | Semiconductor device comprising a semiconductor chip stack and method for producing the same | Oct 1, 2007 | Issued |
Array
(
[id] => 4743429
[patent_doc_number] => 20080088030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'ATTACHING AND INTERCONNECTING DIES TO A SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/863443
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 7601
[patent_no_of_claims] => 46
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[pdf_file] => publications/A1/0088/20080088030.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863443
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863443 | ATTACHING AND INTERCONNECTING DIES TO A SUBSTRATE | Sep 27, 2007 | Abandoned |
Array
(
[id] => 5425846
[patent_doc_number] => 20090085156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'METAL SURFACE TREATMENTS FOR UNIFORMLY GROWING DIELECTRIC LAYERS'
[patent_app_type] => utility
[patent_app_number] => 11/864904
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20090085156.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864904
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864904 | METAL SURFACE TREATMENTS FOR UNIFORMLY GROWING DIELECTRIC LAYERS | Sep 27, 2007 | Abandoned |
Array
(
[id] => 4941822
[patent_doc_number] => 20080079145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'POWER SEMICONDUCTOR ARRANGEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/863463
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => publications/A1/0079/20080079145.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863463
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863463 | Power semiconductor arrangement | Sep 27, 2007 | Issued |
Array
(
[id] => 5425745
[patent_doc_number] => 20090085055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Method for Growing an Epitaxial Layer'
[patent_app_type] => utility
[patent_app_number] => 11/863074
[patent_app_country] => US
[patent_app_date] => 2007-09-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0085/20090085055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863074
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863074 | Method for Growing an Epitaxial Layer | Sep 26, 2007 | Abandoned |
Array
(
[id] => 5425899
[patent_doc_number] => 20090085209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/862744
[patent_app_country] => US
[patent_app_date] => 2007-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0085/20090085209.pdf
[firstpage_image] =>[orig_patent_app_number] => 11862744
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/862744 | Semiconductor device with copper wirebond sites and methods of making same | Sep 26, 2007 | Issued |
Array
(
[id] => 5518502
[patent_doc_number] => 20090026483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-29
[patent_title] => 'HIGH-POWER LED PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 11/861993
[patent_app_country] => US
[patent_app_date] => 2007-09-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0026/20090026483.pdf
[firstpage_image] =>[orig_patent_app_number] => 11861993
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861993 | HIGH-POWER LED PACKAGE | Sep 25, 2007 | Abandoned |
Array
(
[id] => 4919380
[patent_doc_number] => 20080067692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'SEMICONDUCTOR DEVICES HAVING CONTACT PAD PROTECTION FOR REDUCED ELECTRICAL FAILURES AND METHODS OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/854093
[patent_app_country] => US
[patent_app_date] => 2007-09-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0067/20080067692.pdf
[firstpage_image] =>[orig_patent_app_number] => 11854093
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/854093 | SEMICONDUCTOR DEVICES HAVING CONTACT PAD PROTECTION FOR REDUCED ELECTRICAL FAILURES AND METHODS OF FABRICATING THE SAME | Sep 11, 2007 | Abandoned |
Array
(
[id] => 4701915
[patent_doc_number] => 20080061437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'Packaging board, semiconductor module, and portable apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/847933
[patent_app_country] => US
[patent_app_date] => 2007-08-30
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20080061437.pdf
[firstpage_image] =>[orig_patent_app_number] => 11847933
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847933 | Packaging board, semiconductor module, and portable apparatus | Aug 29, 2007 | Issued |
Array
(
[id] => 5319889
[patent_doc_number] => 20090057879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'STRUCTURE AND PROCESS FOR ELECTRICAL INTERCONNECT AND THERMAL MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/846253
[patent_app_country] => US
[patent_app_date] => 2007-08-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0057/20090057879.pdf
[firstpage_image] =>[orig_patent_app_number] => 11846253
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/846253 | Structure and process for electrical interconnect and thermal management | Aug 27, 2007 | Issued |