Search

Leslie Pilar Cruz

Examiner (ID: 7194, Phone: (571)272-8599 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
538
Issued Applications
372
Pending Applications
2
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5116809 [patent_doc_number] => 20070138523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Transistor, memory cell, memory cell array and method of forming a memory cell array' [patent_app_type] => utility [patent_app_number] => 11/300853 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6891 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138523.pdf [firstpage_image] =>[orig_patent_app_number] => 11300853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/300853
Transistor, memory cell, memory cell array and method of forming a memory cell array Dec 14, 2005 Issued
Array ( [id] => 840753 [patent_doc_number] => 07391085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/299773 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6795 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391085.pdf [firstpage_image] =>[orig_patent_app_number] => 11299773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/299773
Semiconductor device Dec 12, 2005 Issued
Array ( [id] => 5038170 [patent_doc_number] => 20070090452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/299544 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090452.pdf [firstpage_image] =>[orig_patent_app_number] => 11299544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/299544
Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same Dec 11, 2005 Abandoned
Array ( [id] => 5250577 [patent_doc_number] => 20070132033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'High voltage CMOS devices' [patent_app_type] => utility [patent_app_number] => 11/301203 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3572 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132033.pdf [firstpage_image] =>[orig_patent_app_number] => 11301203 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301203
High voltage CMOS devices Dec 11, 2005 Issued
Array ( [id] => 5250532 [patent_doc_number] => 20070131988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'CMOS image sensor devices and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/298694 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20070131988.pdf [firstpage_image] =>[orig_patent_app_number] => 11298694 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/298694
CMOS image sensor devices and fabrication method thereof Dec 11, 2005 Abandoned
Array ( [id] => 5908782 [patent_doc_number] => 20060124933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Organic light emitting display device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/297343 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20060124933.pdf [firstpage_image] =>[orig_patent_app_number] => 11297343 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297343
Organic light emitting display device and method of fabricating the same Dec 8, 2005 Issued
Array ( [id] => 363836 [patent_doc_number] => 07482651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Enhanced multi-bit non-volatile memory device with resonant tunnel barrier' [patent_app_type] => utility [patent_app_number] => 11/298884 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5709 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482651.pdf [firstpage_image] =>[orig_patent_app_number] => 11298884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/298884
Enhanced multi-bit non-volatile memory device with resonant tunnel barrier Dec 8, 2005 Issued
Array ( [id] => 5652731 [patent_doc_number] => 20060138466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Layout of semiconductor memory device and method of controlling capacitance of dummy cell' [patent_app_type] => utility [patent_app_number] => 11/296843 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4524 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138466.pdf [firstpage_image] =>[orig_patent_app_number] => 11296843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296843
Layout of semiconductor memory device and method of controlling capacitance of dummy cell Dec 5, 2005 Issued
Array ( [id] => 547711 [patent_doc_number] => 07166908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Optical device' [patent_app_type] => utility [patent_app_number] => 11/244083 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 11802 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166908.pdf [firstpage_image] =>[orig_patent_app_number] => 11244083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244083
Optical device Oct 5, 2005 Issued
Array ( [id] => 5718536 [patent_doc_number] => 20060071309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/236563 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3462 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071309.pdf [firstpage_image] =>[orig_patent_app_number] => 11236563 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/236563
Semiconductor device Sep 27, 2005 Issued
Array ( [id] => 908148 [patent_doc_number] => 07332753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Semiconductor device, wafer and method of designing and manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/235364 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 7260 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332753.pdf [firstpage_image] =>[orig_patent_app_number] => 11235364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235364
Semiconductor device, wafer and method of designing and manufacturing the same Sep 26, 2005 Issued
Array ( [id] => 5718465 [patent_doc_number] => 20060071238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Power module' [patent_app_type] => utility [patent_app_number] => 11/234763 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2421 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071238.pdf [firstpage_image] =>[orig_patent_app_number] => 11234763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/234763
Power module Sep 22, 2005 Issued
Array ( [id] => 5104469 [patent_doc_number] => 20070063344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Chip package structure and bumping process' [patent_app_type] => utility [patent_app_number] => 11/234774 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2902 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063344.pdf [firstpage_image] =>[orig_patent_app_number] => 11234774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/234774
Chip package structure and bumping process Sep 21, 2005 Abandoned
Array ( [id] => 386989 [patent_doc_number] => 07304358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'MOS transistor with a deformable gate' [patent_app_type] => utility [patent_app_number] => 11/227624 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2638 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304358.pdf [firstpage_image] =>[orig_patent_app_number] => 11227624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227624
MOS transistor with a deformable gate Sep 14, 2005 Issued
Array ( [id] => 5898171 [patent_doc_number] => 20060043404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Cap for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/216404 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4524 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043404.pdf [firstpage_image] =>[orig_patent_app_number] => 11216404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216404
Cap for semiconductor device Aug 30, 2005 Issued
Array ( [id] => 5719211 [patent_doc_number] => 20060071984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/213864 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13042 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071984.pdf [firstpage_image] =>[orig_patent_app_number] => 11213864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213864
Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus Aug 29, 2005 Issued
Array ( [id] => 5708175 [patent_doc_number] => 20060049519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/211764 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5596 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049519.pdf [firstpage_image] =>[orig_patent_app_number] => 11211764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211764
Semiconductor device and method for manufacturing semiconductor device Aug 25, 2005 Abandoned
Array ( [id] => 5145652 [patent_doc_number] => 20070045706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Combined volatile and non-volatile memory device with graded composition insulator stack' [patent_app_type] => utility [patent_app_number] => 11/210539 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6426 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045706.pdf [firstpage_image] =>[orig_patent_app_number] => 11210539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210539
Combined volatile and non-volatile memory device with graded composition insulator stack Aug 23, 2005 Issued
Array ( [id] => 5152128 [patent_doc_number] => 20070035010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Circuit substrate' [patent_app_type] => utility [patent_app_number] => 11/199884 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1476 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20070035010.pdf [firstpage_image] =>[orig_patent_app_number] => 11199884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199884
Circuit substrate Aug 8, 2005 Abandoned
Array ( [id] => 5049117 [patent_doc_number] => 20070029661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Power plane design and jumper wire bond for voltage drop minimization' [patent_app_type] => utility [patent_app_number] => 11/198543 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20070029661.pdf [firstpage_image] =>[orig_patent_app_number] => 11198543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198543
Power plane design and jumper wire bond for voltage drop minimization Aug 3, 2005 Abandoned
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