Search

Leslie Pilar Cruz

Examiner (ID: 7194, Phone: (571)272-8599 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
538
Issued Applications
372
Pending Applications
2
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 484470 [patent_doc_number] => 07221045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Flat chip semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/133613 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3086 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221045.pdf [firstpage_image] =>[orig_patent_app_number] => 11133613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133613
Flat chip semiconductor device and manufacturing method thereof May 19, 2005 Issued
Array ( [id] => 7043442 [patent_doc_number] => 20050248037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Flip-chip package substrate with a high-density layout' [patent_app_type] => utility [patent_app_number] => 11/123204 [patent_app_country] => US [patent_app_date] => 2005-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248037.pdf [firstpage_image] =>[orig_patent_app_number] => 11123204 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/123204
Flip-chip package substrate with a high-density layout May 5, 2005 Abandoned
Array ( [id] => 7183427 [patent_doc_number] => 20050161794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/080414 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21655 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161794.pdf [firstpage_image] =>[orig_patent_app_number] => 11080414 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080414
Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate Mar 15, 2005 Abandoned
11/080483 Semiconductor package and stack arrangement thereof Mar 15, 2005 Abandoned
Array ( [id] => 6968406 [patent_doc_number] => 20050235242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Semiconductor integraged circuit device and method of routing interconnections for semiconductor IC device' [patent_app_type] => utility [patent_app_number] => 11/080513 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20050235242.pdf [firstpage_image] =>[orig_patent_app_number] => 11080513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080513
Semiconductor integraged circuit device and method of routing interconnections for semiconductor IC device Mar 15, 2005 Abandoned
Array ( [id] => 6955733 [patent_doc_number] => 20050212103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Semiconductor device designed to produce no resonance of loop due to ultrasonic vibration, semiconductor design apparatus and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/079333 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4429 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212103.pdf [firstpage_image] =>[orig_patent_app_number] => 11079333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/079333
Semiconductor device designed to produce no resonance of loop due to ultrasonic vibration, semiconductor design apparatus and method of manufacturing semiconductor device Mar 14, 2005 Abandoned
Array ( [id] => 651297 [patent_doc_number] => 07112875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-26 [patent_title] => 'Secure digital memory card using land grid array structure' [patent_app_type] => utility [patent_app_number] => 11/060264 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 5369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112875.pdf [firstpage_image] =>[orig_patent_app_number] => 11060264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060264
Secure digital memory card using land grid array structure Feb 16, 2005 Issued
Array ( [id] => 415598 [patent_doc_number] => 07279784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/049863 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279784.pdf [firstpage_image] =>[orig_patent_app_number] => 11049863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049863
Semiconductor package Feb 3, 2005 Issued
Array ( [id] => 7236878 [patent_doc_number] => 20050140024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Semiconductor device, manufacturing method thereof and electronic equipment' [patent_app_type] => utility [patent_app_number] => 11/023094 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3533 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140024.pdf [firstpage_image] =>[orig_patent_app_number] => 11023094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/023094
Semiconductor device, manufacturing method thereof and electronic equipment Dec 21, 2004 Abandoned
Array ( [id] => 578950 [patent_doc_number] => 07459768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Semiconductor wafer and dicing method' [patent_app_type] => utility [patent_app_number] => 11/018984 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4665 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459768.pdf [firstpage_image] =>[orig_patent_app_number] => 11018984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018984
Semiconductor wafer and dicing method Dec 20, 2004 Issued
Array ( [id] => 5049079 [patent_doc_number] => 20070029623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Dual-gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 10/580433 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20070029623.pdf [firstpage_image] =>[orig_patent_app_number] => 10580433 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/580433
Dual-gate field effect transistor Dec 5, 2004 Abandoned
Array ( [id] => 6936577 [patent_doc_number] => 20050110138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'High Speed Electrical On-Chip Interconnects and Method of Manufacturing' [patent_app_type] => utility [patent_app_number] => 10/904723 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110138.pdf [firstpage_image] =>[orig_patent_app_number] => 10904723 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904723
High Speed Electrical On-Chip Interconnects and Method of Manufacturing Nov 23, 2004 Abandoned
Array ( [id] => 6936567 [patent_doc_number] => 20050110128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Highly reliable stack type semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/993693 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110128.pdf [firstpage_image] =>[orig_patent_app_number] => 10993693 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/993693
Highly reliable stack type semiconductor package Nov 18, 2004 Abandoned
Array ( [id] => 548590 [patent_doc_number] => 07170162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Chip embedded package structure' [patent_app_type] => utility [patent_app_number] => 10/994043 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2922 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170162.pdf [firstpage_image] =>[orig_patent_app_number] => 10994043 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994043
Chip embedded package structure Nov 17, 2004 Issued
Array ( [id] => 678337 [patent_doc_number] => 07088586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Techniques for cooling a circuit board component within an environment with little or no forced convection airflow' [patent_app_type] => utility [patent_app_number] => 10/988713 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2816 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088586.pdf [firstpage_image] =>[orig_patent_app_number] => 10988713 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988713
Techniques for cooling a circuit board component within an environment with little or no forced convection airflow Nov 14, 2004 Issued
Array ( [id] => 668865 [patent_doc_number] => 07095099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Low profile package having multiple die' [patent_app_type] => utility [patent_app_number] => 10/988443 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3697 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095099.pdf [firstpage_image] =>[orig_patent_app_number] => 10988443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988443
Low profile package having multiple die Nov 11, 2004 Issued
Array ( [id] => 443743 [patent_doc_number] => 07256489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 10/979563 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3269 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256489.pdf [firstpage_image] =>[orig_patent_app_number] => 10979563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979563
Semiconductor apparatus Nov 1, 2004 Issued
Array ( [id] => 476714 [patent_doc_number] => 07227268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Placement of sacrificial solder balls underneath the PBGA substrate' [patent_app_type] => utility [patent_app_number] => 10/977263 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5117 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227268.pdf [firstpage_image] =>[orig_patent_app_number] => 10977263 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/977263
Placement of sacrificial solder balls underneath the PBGA substrate Oct 28, 2004 Issued
Array ( [id] => 5892567 [patent_doc_number] => 20060001104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Semiconductor device having STI with nitride liner' [patent_app_type] => utility [patent_app_number] => 10/972326 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6488 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001104.pdf [firstpage_image] =>[orig_patent_app_number] => 10972326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/972326
Semiconductor device having STI with nitride liner and UV light shielding film Oct 25, 2004 Issued
Array ( [id] => 760482 [patent_doc_number] => 07015823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-21 [patent_title] => 'Tamper resistant circuit boards' [patent_app_type] => utility [patent_app_number] => 10/966593 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4245 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015823.pdf [firstpage_image] =>[orig_patent_app_number] => 10966593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/966593
Tamper resistant circuit boards Oct 14, 2004 Issued
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