
Leslie Pilar Cruz
Examiner (ID: 15251, Phone: (571)272-8599 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 538 |
| Issued Applications | 372 |
| Pending Applications | 2 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8604003
[patent_doc_number] => 20130009315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY'
[patent_app_type] => utility
[patent_app_number] => 11/899842
[patent_app_country] => US
[patent_app_date] => 2007-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4559
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11899842
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/899842 | Interconnect structures with engineered dielectrics with nanocolumnar porosity | Sep 6, 2007 | Issued |
Array
(
[id] => 7967681
[patent_doc_number] => 07939879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/896800
[patent_app_country] => US
[patent_app_date] => 2007-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 65
[patent_no_of_words] => 27049
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/939/07939879.pdf
[firstpage_image] =>[orig_patent_app_number] => 11896800
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/896800 | Semiconductor device | Sep 5, 2007 | Issued |
Array
(
[id] => 4692808
[patent_doc_number] => 20080085579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-10
[patent_title] => 'Semiconductor structure with high-voltage sustaining capability and fabrication method of the same'
[patent_app_type] => utility
[patent_app_number] => 11/896883
[patent_app_country] => US
[patent_app_date] => 2007-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4353
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20080085579.pdf
[firstpage_image] =>[orig_patent_app_number] => 11896883
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/896883 | Semiconductor structure with high-voltage sustaining capability and fabrication method of the same | Sep 5, 2007 | Issued |
Array
(
[id] => 4564708
[patent_doc_number] => 07821804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-26
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/896802
[patent_app_country] => US
[patent_app_date] => 2007-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 9485
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/821/07821804.pdf
[firstpage_image] =>[orig_patent_app_number] => 11896802
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/896802 | Semiconductor integrated circuit | Sep 5, 2007 | Issued |
Array
(
[id] => 4768839
[patent_doc_number] => 20080054495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'FUNCTIONAL DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/849584
[patent_app_country] => US
[patent_app_date] => 2007-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5981
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20080054495.pdf
[firstpage_image] =>[orig_patent_app_number] => 11849584
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849584 | Functional device, semiconductor device, and electronic device | Sep 3, 2007 | Issued |
Array
(
[id] => 803610
[patent_doc_number] => 07423314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Semiconductor memory device and method for the same'
[patent_app_type] => utility
[patent_app_number] => 11/848944
[patent_app_country] => US
[patent_app_date] => 2007-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 47
[patent_no_of_words] => 8345
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/423/07423314.pdf
[firstpage_image] =>[orig_patent_app_number] => 11848944
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/848944 | Semiconductor memory device and method for the same | Aug 30, 2007 | Issued |
Array
(
[id] => 5493343
[patent_doc_number] => 20090261371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-22
[patent_title] => 'Light-Emitting Device'
[patent_app_type] => utility
[patent_app_number] => 12/442366
[patent_app_country] => US
[patent_app_date] => 2007-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3992
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20090261371.pdf
[firstpage_image] =>[orig_patent_app_number] => 12442366
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/442366 | Light-emitting device | Aug 27, 2007 | Issued |
Array
(
[id] => 5364758
[patent_doc_number] => 20090302317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'SWITCHING DEVICE AND TESTING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/442500
[patent_app_country] => US
[patent_app_date] => 2007-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8209
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0302/20090302317.pdf
[firstpage_image] =>[orig_patent_app_number] => 12442500
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/442500 | Switching device and testing apparatus | Aug 21, 2007 | Issued |
Array
(
[id] => 830484
[patent_doc_number] => 07400039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-15
[patent_title] => 'Semiconductor device and semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 11/841014
[patent_app_country] => US
[patent_app_date] => 2007-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5861
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/400/07400039.pdf
[firstpage_image] =>[orig_patent_app_number] => 11841014
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/841014 | Semiconductor device and semiconductor package | Aug 19, 2007 | Issued |
Array
(
[id] => 34667
[patent_doc_number] => 07786543
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-31
[patent_title] => 'CDS capable sensor with photon sensing layer on active pixel circuit'
[patent_app_type] => utility
[patent_app_number] => 11/893828
[patent_app_country] => US
[patent_app_date] => 2007-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8629
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/786/07786543.pdf
[firstpage_image] =>[orig_patent_app_number] => 11893828
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/893828 | CDS capable sensor with photon sensing layer on active pixel circuit | Aug 16, 2007 | Issued |
Array
(
[id] => 4768709
[patent_doc_number] => 20080054365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Semiconductor device and manufacturing method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/889766
[patent_app_country] => US
[patent_app_date] => 2007-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 17274
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20080054365.pdf
[firstpage_image] =>[orig_patent_app_number] => 11889766
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/889766 | Semiconductor device having NMOSFET and PMOSFET and manufacturing method therefor | Aug 15, 2007 | Issued |
Array
(
[id] => 5163088
[patent_doc_number] => 20070284669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING'
[patent_app_type] => utility
[patent_app_number] => 11/838934
[patent_app_country] => US
[patent_app_date] => 2007-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6128
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0284/20070284669.pdf
[firstpage_image] =>[orig_patent_app_number] => 11838934
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/838934 | METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING | Aug 14, 2007 | Abandoned |
Array
(
[id] => 4701909
[patent_doc_number] => 20080061431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'POWER SEMICONDUCTOR MODULE'
[patent_app_type] => utility
[patent_app_number] => 11/834724
[patent_app_country] => US
[patent_app_date] => 2007-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8842
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20080061431.pdf
[firstpage_image] =>[orig_patent_app_number] => 11834724
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/834724 | Power semiconductor module | Aug 6, 2007 | Issued |
Array
(
[id] => 5358031
[patent_doc_number] => 20090032825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'Structure Of LED-Based Display Module And Method For Manufacturing The Same'
[patent_app_type] => utility
[patent_app_number] => 11/832654
[patent_app_country] => US
[patent_app_date] => 2007-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2006
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20090032825.pdf
[firstpage_image] =>[orig_patent_app_number] => 11832654
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/832654 | Structure Of LED-Based Display Module And Method For Manufacturing The Same | Aug 1, 2007 | Abandoned |
Array
(
[id] => 5358067
[patent_doc_number] => 20090032861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'NONVOLATILE MEMORIES WITH CHARGE TRAPPING LAYERS CONTAINING SILICON NITRIDE WITH GERMANIUM OR PHOSPHORUS'
[patent_app_type] => utility
[patent_app_number] => 11/830524
[patent_app_country] => US
[patent_app_date] => 2007-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2336
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20090032861.pdf
[firstpage_image] =>[orig_patent_app_number] => 11830524
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/830524 | NONVOLATILE MEMORIES WITH CHARGE TRAPPING LAYERS CONTAINING SILICON NITRIDE WITH GERMANIUM OR PHOSPHORUS | Jul 29, 2007 | Abandoned |
Array
(
[id] => 5358096
[patent_doc_number] => 20090032890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'MULTILAYER DIELECTRIC'
[patent_app_type] => utility
[patent_app_number] => 11/830533
[patent_app_country] => US
[patent_app_date] => 2007-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8673
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20090032890.pdf
[firstpage_image] =>[orig_patent_app_number] => 11830533
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/830533 | Multilayer dielectric | Jul 29, 2007 | Issued |
Array
(
[id] => 4443540
[patent_doc_number] => 07928481
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Method and layout of semiconductor device with reduced parasitics'
[patent_app_type] => utility
[patent_app_number] => 11/828944
[patent_app_country] => US
[patent_app_date] => 2007-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3286
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/928/07928481.pdf
[firstpage_image] =>[orig_patent_app_number] => 11828944
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/828944 | Method and layout of semiconductor device with reduced parasitics | Jul 25, 2007 | Issued |
Array
(
[id] => 4443540
[patent_doc_number] => 07928481
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Method and layout of semiconductor device with reduced parasitics'
[patent_app_type] => utility
[patent_app_number] => 11/828944
[patent_app_country] => US
[patent_app_date] => 2007-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3286
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/928/07928481.pdf
[firstpage_image] =>[orig_patent_app_number] => 11828944
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/828944 | Method and layout of semiconductor device with reduced parasitics | Jul 25, 2007 | Issued |
Array
(
[id] => 4443540
[patent_doc_number] => 07928481
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Method and layout of semiconductor device with reduced parasitics'
[patent_app_type] => utility
[patent_app_number] => 11/828944
[patent_app_country] => US
[patent_app_date] => 2007-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3286
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/928/07928481.pdf
[firstpage_image] =>[orig_patent_app_number] => 11828944
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/828944 | Method and layout of semiconductor device with reduced parasitics | Jul 25, 2007 | Issued |
Array
(
[id] => 4443540
[patent_doc_number] => 07928481
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Method and layout of semiconductor device with reduced parasitics'
[patent_app_type] => utility
[patent_app_number] => 11/828944
[patent_app_country] => US
[patent_app_date] => 2007-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3286
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/928/07928481.pdf
[firstpage_image] =>[orig_patent_app_number] => 11828944
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/828944 | Method and layout of semiconductor device with reduced parasitics | Jul 25, 2007 | Issued |