Search

Liang Dong

Examiner (ID: 2440, Phone: (571)270-0479 , Office: P/3724 )

Most Active Art Unit
3724
Art Unit(s)
3724
Total Applications
623
Issued Applications
285
Pending Applications
107
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18440146 [patent_doc_number] => 20230187441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT FLYOVER STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/548027 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548027
INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT FLYOVER STRUCTURE Dec 9, 2021 Pending
Array ( [id] => 17506679 [patent_doc_number] => 20220099782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SYNCHRONIZATION OF UNSTABLE SIGNAL SOURCES FOR USE IN A PHASE STABLE INSTRUMENT [patent_app_type] => utility [patent_app_number] => 17/548381 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548381
Synchronization of unstable signal sources for use in a phase stable instrument Dec 9, 2021 Issued
Array ( [id] => 19610907 [patent_doc_number] => 12159788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Method of forming structures for threshold voltage control [patent_app_type] => utility [patent_app_number] => 17/546186 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12877 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546186
Method of forming structures for threshold voltage control Dec 8, 2021 Issued
Array ( [id] => 18494216 [patent_doc_number] => 11699637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Vertically stacked transistor devices with isolation wall structures containing an electrical conductor [patent_app_type] => utility [patent_app_number] => 17/547066 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 9442 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547066
Vertically stacked transistor devices with isolation wall structures containing an electrical conductor Dec 8, 2021 Issued
Array ( [id] => 17486265 [patent_doc_number] => 20220093769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE [patent_app_type] => utility [patent_app_number] => 17/544652 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544652
Method for fabricating semiconductor device with programmable feature Dec 6, 2021 Issued
Array ( [id] => 18927035 [patent_doc_number] => 20240030039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => METALLIZATION OF SEMICONDUCTOR WAFER [patent_app_type] => utility [patent_app_number] => 18/255516 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18255516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/255516
METALLIZATION OF SEMICONDUCTOR WAFER Nov 30, 2021 Pending
Array ( [id] => 19906508 [patent_doc_number] => 12283526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Edge fin trim process [patent_app_type] => utility [patent_app_number] => 17/521610 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 4433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521610
Edge fin trim process Nov 7, 2021 Issued
Array ( [id] => 17795558 [patent_doc_number] => 20220254650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/517304 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517304
Semiconductor device and a method of manufacturing the semiconductor device Nov 1, 2021 Issued
Array ( [id] => 18345186 [patent_doc_number] => 20230133296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => INTEGRATING STANDARD-GATE TRANSISTORS AND EXTENDED-GATE TRANSISTORS ON THE SAME SUBSTRATE USING LOW-TEMPERATURE GATE DIELECTRIC TREATMENTS [patent_app_type] => utility [patent_app_number] => 17/512784 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512784
INTEGRATING STANDARD-GATE TRANSISTORS AND EXTENDED-GATE TRANSISTORS ON THE SAME SUBSTRATE USING LOW-TEMPERATURE GATE DIELECTRIC TREATMENTS Oct 27, 2021 Pending
Array ( [id] => 19349514 [patent_doc_number] => 20240258478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => LIGHT-EMITTING SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/040505 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18040505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/040505
Light-emitting substrate, method for manufacturing the same, and display device Oct 26, 2021 Issued
Array ( [id] => 19168534 [patent_doc_number] => 11984448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/509265 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 13875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509265
Semiconductor device Oct 24, 2021 Issued
Array ( [id] => 17963962 [patent_doc_number] => 20220344543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MICRO LIGHT-EMITTING DIODE STRUCTURE AND MICRO LIGHT-EMITTING DIODE DISPLAY PANEL USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/501310 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501310
Micro light-emitting diode structure and micro light-emitting diode display panel using the same Oct 13, 2021 Issued
Array ( [id] => 19926411 [patent_doc_number] => 12300707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Image sensing device [patent_app_type] => utility [patent_app_number] => 17/499698 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4717 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499698
Image sensing device Oct 11, 2021 Issued
Array ( [id] => 17551762 [patent_doc_number] => 20220123104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => CAPACITOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/450520 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450520
Capacitor structure and forming method thereof Oct 10, 2021 Issued
Array ( [id] => 19486699 [patent_doc_number] => 20240334741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/291047 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18291047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/291047
DISPLAY DEVICE Oct 10, 2021 Pending
Array ( [id] => 18286693 [patent_doc_number] => 20230102165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => CONTACT STRUCTURE FORMATION FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/484453 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484453
Contact structure formation for memory devices Sep 23, 2021 Issued
Array ( [id] => 19639642 [patent_doc_number] => 12170257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Three-dimensional memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/480852 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 112 [patent_figures_cnt] => 153 [patent_no_of_words] => 90788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480852
Three-dimensional memory devices and methods for forming the same Sep 20, 2021 Issued
Array ( [id] => 17709172 [patent_doc_number] => 20220209180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/481111 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481111
Display device Sep 20, 2021 Issued
Array ( [id] => 18639567 [patent_doc_number] => 11764190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => 3D stacked compute and memory with copper pillars [patent_app_type] => utility [patent_app_number] => 17/472325 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10390 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472325
3D stacked compute and memory with copper pillars Sep 9, 2021 Issued
Array ( [id] => 18688419 [patent_doc_number] => 11784164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => 3D stacked compute and memory with copper-to-copper hybrid bond [patent_app_type] => utility [patent_app_number] => 17/472308 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 13234 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472308
3D stacked compute and memory with copper-to-copper hybrid bond Sep 9, 2021 Issued
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