Search

Liang Dong

Examiner (ID: 2440, Phone: (571)270-0479 , Office: P/3724 )

Most Active Art Unit
3724
Art Unit(s)
3724
Total Applications
623
Issued Applications
285
Pending Applications
107
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11315714 [patent_doc_number] => 20160351824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/236914 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 22087 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236914
Thin film transistor Aug 14, 2016 Issued
Array ( [id] => 11315729 [patent_doc_number] => 20160351839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'ORGANIC THIN-FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/236907 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 20196 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236907
ORGANIC THIN-FILM TRANSISTOR Aug 14, 2016 Abandoned
Array ( [id] => 11315649 [patent_doc_number] => 20160351759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'LIGHT EMITTING DIODE CHIP HAVING WAVELENGTH CONVERTING LAYER AND METHOD OF FABRICATING THE SAME, AND PACKAGE HAVING THE LIGHT EMITTING DIODE CHIP AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/236125 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14684 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236125
Light emitting diode chip having wavelength converting layer and method of fabricating the same, and package having the light emitting diode chip and method of fabricating the same Aug 11, 2016 Issued
Array ( [id] => 13214965 [patent_doc_number] => 10121860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => BJT structure design for 14nm FinFET device [patent_app_type] => utility [patent_app_number] => 15/236329 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 8545 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236329
BJT structure design for 14nm FinFET device Aug 11, 2016 Issued
Array ( [id] => 12122406 [patent_doc_number] => 20180005992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND A MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/234813 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234813
Semiconductor structure and a manufacturing method thereof Aug 10, 2016 Issued
Array ( [id] => 12335235 [patent_doc_number] => 09947746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Bipolar junction transistor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/234432 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3621 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234432
Bipolar junction transistor device and method for fabricating the same Aug 10, 2016 Issued
Array ( [id] => 11911388 [patent_doc_number] => 09780210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Backside semiconductor growth' [patent_app_type] => utility [patent_app_number] => 15/234889 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 9462 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234889
Backside semiconductor growth Aug 10, 2016 Issued
Array ( [id] => 11315394 [patent_doc_number] => 20160351504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'SEMICONDUCTOR PACKAGE AND MOUNTING STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 15/232959 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232959 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232959
Semiconductor package and mounting structure thereof Aug 9, 2016 Issued
Array ( [id] => 12188756 [patent_doc_number] => 20180047692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'Method and System for Packing Optimization of Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 15/233271 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233271
Method and System for Packing Optimization of Semiconductor Devices Aug 9, 2016 Abandoned
Array ( [id] => 12188751 [patent_doc_number] => 20180047687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SEMICONDUCTOR ASSEMBLY AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 15/233902 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4430 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233902
Semiconductor assembly and method of making same Aug 9, 2016 Issued
Array ( [id] => 13364001 [patent_doc_number] => 20180233540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => PHOTOELECTRIC CONVERSION ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 15/751029 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15751029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/751029
Photoelectric conversion element, imaging device, and electronic apparatus Aug 8, 2016 Issued
Array ( [id] => 11753628 [patent_doc_number] => 09711648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Structure and method for CMP-free III-V isolation' [patent_app_type] => utility [patent_app_number] => 15/232164 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232164 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232164
Structure and method for CMP-free III-V isolation Aug 8, 2016 Issued
Array ( [id] => 13653235 [patent_doc_number] => 09852938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Passivated germanium-on-insulator lateral bipolar transistors [patent_app_type] => utility [patent_app_number] => 15/231087 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4528 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231087 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/231087
Passivated germanium-on-insulator lateral bipolar transistors Aug 7, 2016 Issued
Array ( [id] => 11638048 [patent_doc_number] => 09660034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-23 [patent_title] => 'Electronic chip comprising transistors with front and back gates' [patent_app_type] => utility [patent_app_number] => 15/229746 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3571 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229746 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/229746
Electronic chip comprising transistors with front and back gates Aug 4, 2016 Issued
Array ( [id] => 12177147 [patent_doc_number] => 20180036083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'PATELLA IMPLANT PLANNING' [patent_app_type] => utility [patent_app_number] => 15/227433 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227433 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227433
Patella implant planning Aug 2, 2016 Issued
Array ( [id] => 12499008 [patent_doc_number] => 09997631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Methods for reducing contact resistance in semiconductors manufacturing process [patent_app_type] => utility [patent_app_number] => 15/226321 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 11625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/226321
Methods for reducing contact resistance in semiconductors manufacturing process Aug 1, 2016 Issued
Array ( [id] => 13030937 [patent_doc_number] => 10038093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => FIN field effect transistors having liners between device isolation layers and active areas of the device [patent_app_type] => utility [patent_app_number] => 15/223332 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15223332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/223332
FIN field effect transistors having liners between device isolation layers and active areas of the device Jul 28, 2016 Issued
Array ( [id] => 11564924 [patent_doc_number] => 09627521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Trench IGBT with tub-shaped floating P-well and hole drains to P-body regions' [patent_app_type] => utility [patent_app_number] => 15/222762 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6248 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222762
Trench IGBT with tub-shaped floating P-well and hole drains to P-body regions Jul 27, 2016 Issued
Array ( [id] => 11918431 [patent_doc_number] => 09786624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 15/222155 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222155 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222155
Semiconductor package Jul 27, 2016 Issued
Array ( [id] => 11862028 [patent_doc_number] => 09741720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Higher ‘K’ gate dielectric cap for replacement metal gate (RMG) FINFET devices' [patent_app_type] => utility [patent_app_number] => 15/219967 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4951 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219967 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219967
Higher ‘K’ gate dielectric cap for replacement metal gate (RMG) FINFET devices Jul 25, 2016 Issued
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