Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 394483 [patent_doc_number] => 07298184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit' [patent_app_type] => utility [patent_app_number] => 11/513655 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298184.pdf [firstpage_image] =>[orig_patent_app_number] => 11513655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513655
Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit Aug 30, 2006 Issued
Array ( [id] => 7603007 [patent_doc_number] => 07236027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof' [patent_app_type] => utility [patent_app_number] => 11/463897 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3849 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236027.pdf [firstpage_image] =>[orig_patent_app_number] => 11463897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463897
Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof Aug 10, 2006 Issued
Array ( [id] => 5659572 [patent_doc_number] => 20060250168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Highly configurable PLL architecture for programmable logic' [patent_app_type] => utility [patent_app_number] => 11/486565 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6138 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250168.pdf [firstpage_image] =>[orig_patent_app_number] => 11486565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486565
Highly configurable PLL architecture for programmable logic Jul 12, 2006 Issued
Array ( [id] => 920269 [patent_doc_number] => 07321250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/440073 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5810 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321250.pdf [firstpage_image] =>[orig_patent_app_number] => 11440073 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/440073
Integrated circuit device May 24, 2006 Issued
Array ( [id] => 5757835 [patent_doc_number] => 20060208780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Delay-locked loop with feedback compensation' [patent_app_type] => utility [patent_app_number] => 11/439685 [patent_app_country] => US [patent_app_date] => 2006-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20060208780.pdf [firstpage_image] =>[orig_patent_app_number] => 11439685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/439685
Delay-locked loop with feedback compensation May 23, 2006 Issued
Array ( [id] => 440551 [patent_doc_number] => 07259608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 11/433216 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 5859 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259608.pdf [firstpage_image] =>[orig_patent_app_number] => 11433216 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433216
System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal May 10, 2006 Issued
Array ( [id] => 448000 [patent_doc_number] => 07253672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 11/430471 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6441 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253672.pdf [firstpage_image] =>[orig_patent_app_number] => 11430471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430471
System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal May 7, 2006 Issued
Array ( [id] => 5703554 [patent_doc_number] => 20060192601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method and apparatus for digital phase generation at high frequencies' [patent_app_type] => utility [patent_app_number] => 11/413790 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7719 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20060192601.pdf [firstpage_image] =>[orig_patent_app_number] => 11413790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413790
Method and apparatus for digital phase generation at high frequencies Apr 27, 2006 Issued
Array ( [id] => 412164 [patent_doc_number] => 07282969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Low divide ratio programmable frequency divider and method thereof' [patent_app_type] => utility [patent_app_number] => 11/380917 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6775 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282969.pdf [firstpage_image] =>[orig_patent_app_number] => 11380917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380917
Low divide ratio programmable frequency divider and method thereof Apr 27, 2006 Issued
90/008014 HIGH-EFFICIENCY ADAPTIVE DC/AC CONVERTER Apr 18, 2006 Issued
Array ( [id] => 383507 [patent_doc_number] => 07307459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/378695 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307459.pdf [firstpage_image] =>[orig_patent_app_number] => 11378695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378695
Programmable phase-locked loop circuitry for programmable logic device Mar 15, 2006 Issued
Array ( [id] => 4975224 [patent_doc_number] => 20070216454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'FAST LOCKING MECHANISM FOR DELAY LOCK LOOPS AND PHASE LOCK LOOPS' [patent_app_type] => utility [patent_app_number] => 11/374808 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20070216454.pdf [firstpage_image] =>[orig_patent_app_number] => 11374808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/374808
Fast locking mechanism for delay lock loops and phase lock loops Mar 13, 2006 Issued
Array ( [id] => 5869806 [patent_doc_number] => 20060164127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'High speed peak amplitude comparator' [patent_app_type] => utility [patent_app_number] => 11/369604 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2546 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164127.pdf [firstpage_image] =>[orig_patent_app_number] => 11369604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/369604
High speed peak amplitude comparator Mar 5, 2006 Abandoned
90/007922 PARELLEL PROCESSOR SYSTEM FOR PROCESSING NATURAL CONCURRENCIES AND METHOD THEREFOR Feb 8, 2006 Issued
Array ( [id] => 504362 [patent_doc_number] => 07205802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Apparatus and method for controlling a delay chain' [patent_app_type] => utility [patent_app_number] => 11/349516 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4015 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205802.pdf [firstpage_image] =>[orig_patent_app_number] => 11349516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/349516
Apparatus and method for controlling a delay chain Feb 2, 2006 Issued
Array ( [id] => 5175593 [patent_doc_number] => 20070176651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Circuits for locally generating non-integral divided clocks with centralized state machines' [patent_app_type] => utility [patent_app_number] => 11/341032 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2960 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176651.pdf [firstpage_image] =>[orig_patent_app_number] => 11341032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341032
Circuits for locally generating non-integral divided clocks with centralized state machines Jan 26, 2006 Issued
Array ( [id] => 7603001 [patent_doc_number] => 07236033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'System and method for detecting processing speed of integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/340755 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4269 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236033.pdf [firstpage_image] =>[orig_patent_app_number] => 11340755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/340755
System and method for detecting processing speed of integrated circuit Jan 26, 2006 Issued
Array ( [id] => 5665118 [patent_doc_number] => 20060170468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'PLL circuit and program for same' [patent_app_type] => utility [patent_app_number] => 11/340633 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9027 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170468.pdf [firstpage_image] =>[orig_patent_app_number] => 11340633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/340633
PLL circuit and program for same Jan 26, 2006 Issued
Array ( [id] => 918698 [patent_doc_number] => 07323915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Delay locked loop with selectable delay' [patent_app_type] => utility [patent_app_number] => 11/335749 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7427 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323915.pdf [firstpage_image] =>[orig_patent_app_number] => 11335749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335749
Delay locked loop with selectable delay Jan 18, 2006 Issued
Array ( [id] => 5020069 [patent_doc_number] => 20070146035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Receive clock deskewing method, apparatus, and system' [patent_app_type] => utility [patent_app_number] => 11/319689 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3448 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20070146035.pdf [firstpage_image] =>[orig_patent_app_number] => 11319689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319689
Receive clock deskewing method, apparatus, and system Dec 27, 2005 Issued
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