
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 394483
[patent_doc_number] => 07298184
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit'
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[patent_app_number] => 11/513655
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[pdf_file] => patents/07/298/07298184.pdf
[firstpage_image] =>[orig_patent_app_number] => 11513655
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/513655 | Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit | Aug 30, 2006 | Issued |
Array
(
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[patent_doc_number] => 07236027
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[patent_issue_date] => 2007-06-26
[patent_title] => 'Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/463897 | Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof | Aug 10, 2006 | Issued |
Array
(
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[patent_issue_date] => 2006-11-09
[patent_title] => 'Highly configurable PLL architecture for programmable logic'
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Array
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[patent_title] => 'Integrated circuit device'
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Array
(
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Array
(
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[patent_title] => 'System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal'
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Array
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[patent_title] => 'System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal'
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Array
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[patent_issue_date] => 2006-08-31
[patent_title] => 'Method and apparatus for digital phase generation at high frequencies'
[patent_app_type] => utility
[patent_app_number] => 11/413790
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/413790 | Method and apparatus for digital phase generation at high frequencies | Apr 27, 2006 | Issued |
Array
(
[id] => 412164
[patent_doc_number] => 07282969
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[patent_issue_date] => 2007-10-16
[patent_title] => 'Low divide ratio programmable frequency divider and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/380917 | Low divide ratio programmable frequency divider and method thereof | Apr 27, 2006 | Issued |
| 90/008014 | HIGH-EFFICIENCY ADAPTIVE DC/AC CONVERTER | Apr 18, 2006 | Issued |
Array
(
[id] => 383507
[patent_doc_number] => 07307459
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[patent_issue_date] => 2007-12-11
[patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/378695 | Programmable phase-locked loop circuitry for programmable logic device | Mar 15, 2006 | Issued |
Array
(
[id] => 4975224
[patent_doc_number] => 20070216454
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[patent_title] => 'FAST LOCKING MECHANISM FOR DELAY LOCK LOOPS AND PHASE LOCK LOOPS'
[patent_app_type] => utility
[patent_app_number] => 11/374808
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Array
(
[id] => 5869806
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[patent_title] => 'High speed peak amplitude comparator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/369604 | High speed peak amplitude comparator | Mar 5, 2006 | Abandoned |
| 90/007922 | PARELLEL PROCESSOR SYSTEM FOR PROCESSING NATURAL CONCURRENCIES AND METHOD THEREFOR | Feb 8, 2006 | Issued |
Array
(
[id] => 504362
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349516 | Apparatus and method for controlling a delay chain | Feb 2, 2006 | Issued |
Array
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[patent_title] => 'Circuits for locally generating non-integral divided clocks with centralized state machines'
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Array
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Array
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