Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5665108 [patent_doc_number] => 20060170458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Output buffer with improved slew rate and method thereof' [patent_app_type] => utility [patent_app_number] => 11/319232 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5268 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170458.pdf [firstpage_image] =>[orig_patent_app_number] => 11319232 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319232
Output buffer with improved slew rate and method thereof Dec 27, 2005 Issued
Array ( [id] => 509201 [patent_doc_number] => 07202716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain' [patent_app_type] => utility [patent_app_number] => 11/320254 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4996 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202716.pdf [firstpage_image] =>[orig_patent_app_number] => 11320254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/320254
Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain Dec 26, 2005 Issued
Array ( [id] => 5054788 [patent_doc_number] => 20070057709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Clock generation circuit and clock generation method' [patent_app_type] => utility [patent_app_number] => 11/312392 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7325 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057709.pdf [firstpage_image] =>[orig_patent_app_number] => 11312392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/312392
Clock generation circuit and clock generation method Dec 20, 2005 Issued
Array ( [id] => 496864 [patent_doc_number] => 07212049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Digital-control-type phase-composing circuit system' [patent_app_type] => utility [patent_app_number] => 11/305037 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2208 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212049.pdf [firstpage_image] =>[orig_patent_app_number] => 11305037 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305037
Digital-control-type phase-composing circuit system Dec 18, 2005 Issued
Array ( [id] => 5805569 [patent_doc_number] => 20060091922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Duty cycle correction' [patent_app_type] => utility [patent_app_number] => 11/300073 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4991 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091922.pdf [firstpage_image] =>[orig_patent_app_number] => 11300073 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/300073
Duty cycle correction Dec 13, 2005 Issued
Array ( [id] => 500714 [patent_doc_number] => 07208986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Measure-controlled delay circuits with reduced phase error' [patent_app_type] => utility [patent_app_number] => 11/293634 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5871 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208986.pdf [firstpage_image] =>[orig_patent_app_number] => 11293634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/293634
Measure-controlled delay circuits with reduced phase error Dec 1, 2005 Issued
Array ( [id] => 425651 [patent_doc_number] => 07271634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-18 [patent_title] => 'Delay-locked loop having a plurality of lock modes' [patent_app_type] => utility [patent_app_number] => 11/286454 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7816 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271634.pdf [firstpage_image] =>[orig_patent_app_number] => 11286454 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286454
Delay-locked loop having a plurality of lock modes Nov 22, 2005 Issued
90/007811 PRECISION OPTICAL MOUNTS Nov 22, 2005 Issued
Array ( [id] => 492312 [patent_doc_number] => 07215165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-08 [patent_title] => 'Clock generating circuit and clock generating method' [patent_app_type] => utility [patent_app_number] => 11/267152 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7037 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215165.pdf [firstpage_image] =>[orig_patent_app_number] => 11267152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267152
Clock generating circuit and clock generating method Nov 6, 2005 Issued
90/007791 MEDICAL X-RAY DIGITIZING AND CHART STORAGE SYSTEM Oct 30, 2005 Issued
Array ( [id] => 532198 [patent_doc_number] => 07183821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-27 [patent_title] => 'Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization' [patent_app_type] => utility [patent_app_number] => 11/257258 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3855 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183821.pdf [firstpage_image] =>[orig_patent_app_number] => 11257258 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257258
Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization Oct 23, 2005 Issued
Array ( [id] => 5878701 [patent_doc_number] => 20060028255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Semiconductor integrated circuit having built-in PLL circuit' [patent_app_type] => utility [patent_app_number] => 11/241995 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9685 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028255.pdf [firstpage_image] =>[orig_patent_app_number] => 11241995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241995
Semiconductor integrated circuit having built-in PLL circuit Oct 3, 2005 Issued
Array ( [id] => 5796869 [patent_doc_number] => 20060033546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Configurable circuit structure having reduced susceptibility to interference when using at least two such circuits to perform like functions' [patent_app_type] => utility [patent_app_number] => 11/239943 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5733 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033546.pdf [firstpage_image] =>[orig_patent_app_number] => 11239943 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239943
Configurable circuit structure having reduced susceptibility to interference when using at least two such circuits to perform like functions Sep 29, 2005 Issued
Array ( [id] => 504399 [patent_doc_number] => 07205810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Skew tolerant phase shift driver with controlled reset pulse width' [patent_app_type] => utility [patent_app_number] => 11/239264 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205810.pdf [firstpage_image] =>[orig_patent_app_number] => 11239264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239264
Skew tolerant phase shift driver with controlled reset pulse width Sep 28, 2005 Issued
Array ( [id] => 532230 [patent_doc_number] => 07183824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme' [patent_app_type] => utility [patent_app_number] => 11/235646 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5836 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183824.pdf [firstpage_image] =>[orig_patent_app_number] => 11235646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235646
Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme Sep 25, 2005 Issued
Array ( [id] => 5796877 [patent_doc_number] => 20060033554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Charge pump circuit' [patent_app_type] => utility [patent_app_number] => 11/234379 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4012 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033554.pdf [firstpage_image] =>[orig_patent_app_number] => 11234379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/234379
Charge pump circuit Sep 25, 2005 Abandoned
Array ( [id] => 5600047 [patent_doc_number] => 20060290392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Clock generators' [patent_app_type] => utility [patent_app_number] => 11/232949 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6071 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20060290392.pdf [firstpage_image] =>[orig_patent_app_number] => 11232949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/232949
Programmable fractional-N clock generators Sep 22, 2005 Issued
Array ( [id] => 509197 [patent_doc_number] => 07202715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'Matched current delay cell and delay locked loop' [patent_app_type] => utility [patent_app_number] => 11/232840 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202715.pdf [firstpage_image] =>[orig_patent_app_number] => 11232840 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/232840
Matched current delay cell and delay locked loop Sep 20, 2005 Issued
Array ( [id] => 513831 [patent_doc_number] => 07199625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-03 [patent_title] => 'Delay locked loop structure providing first and second locked clock signals' [patent_app_type] => utility [patent_app_number] => 11/230896 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 11532 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199625.pdf [firstpage_image] =>[orig_patent_app_number] => 11230896 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230896
Delay locked loop structure providing first and second locked clock signals Sep 19, 2005 Issued
Array ( [id] => 462009 [patent_doc_number] => 07242228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Method and device for generating an output signal having a predetermined phase shift with respect to an input signal' [patent_app_type] => utility [patent_app_number] => 11/227987 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4908 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242228.pdf [firstpage_image] =>[orig_patent_app_number] => 11227987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227987
Method and device for generating an output signal having a predetermined phase shift with respect to an input signal Sep 14, 2005 Issued
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