
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_doc_number] => 20060170458
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[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Output buffer with improved slew rate and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/319232
[patent_app_country] => US
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[pdf_file] => publications/A1/0170/20060170458.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319232 | Output buffer with improved slew rate and method thereof | Dec 27, 2005 | Issued |
Array
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[patent_issue_date] => 2007-04-10
[patent_title] => 'Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain'
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Array
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[patent_title] => 'Clock generation circuit and clock generation method'
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[patent_app_number] => 11/312392
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Array
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[patent_title] => 'Digital-control-type phase-composing circuit system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/305037 | Digital-control-type phase-composing circuit system | Dec 18, 2005 | Issued |
Array
(
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Array
(
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[patent_title] => 'Measure-controlled delay circuits with reduced phase error'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/293634 | Measure-controlled delay circuits with reduced phase error | Dec 1, 2005 | Issued |
Array
(
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[patent_title] => 'Delay-locked loop having a plurality of lock modes'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/286454 | Delay-locked loop having a plurality of lock modes | Nov 22, 2005 | Issued |
| 90/007811 | PRECISION OPTICAL MOUNTS | Nov 22, 2005 | Issued |
Array
(
[id] => 492312
[patent_doc_number] => 07215165
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[patent_issue_date] => 2007-05-08
[patent_title] => 'Clock generating circuit and clock generating method'
[patent_app_type] => utility
[patent_app_number] => 11/267152
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[patent_app_date] => 2005-11-07
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[pdf_file] => patents/07/215/07215165.pdf
[firstpage_image] =>[orig_patent_app_number] => 11267152
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/267152 | Clock generating circuit and clock generating method | Nov 6, 2005 | Issued |
| 90/007791 | MEDICAL X-RAY DIGITIZING AND CHART STORAGE SYSTEM | Oct 30, 2005 | Issued |
Array
(
[id] => 532198
[patent_doc_number] => 07183821
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[patent_issue_date] => 2007-02-27
[patent_title] => 'Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization'
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[patent_app_number] => 11/257258
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/257258 | Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization | Oct 23, 2005 | Issued |
Array
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[id] => 5878701
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[patent_issue_date] => 2006-02-09
[patent_title] => 'Semiconductor integrated circuit having built-in PLL circuit'
[patent_app_type] => utility
[patent_app_number] => 11/241995
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[firstpage_image] =>[orig_patent_app_number] => 11241995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/241995 | Semiconductor integrated circuit having built-in PLL circuit | Oct 3, 2005 | Issued |
Array
(
[id] => 5796869
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[patent_issue_date] => 2006-02-16
[patent_title] => 'Configurable circuit structure having reduced susceptibility to interference when using at least two such circuits to perform like functions'
[patent_app_type] => utility
[patent_app_number] => 11/239943
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Array
(
[id] => 504399
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[patent_title] => 'Skew tolerant phase shift driver with controlled reset pulse width'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/239264 | Skew tolerant phase shift driver with controlled reset pulse width | Sep 28, 2005 | Issued |
Array
(
[id] => 532230
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[patent_title] => 'Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/235646 | Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme | Sep 25, 2005 | Issued |
Array
(
[id] => 5796877
[patent_doc_number] => 20060033554
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[patent_issue_date] => 2006-02-16
[patent_title] => 'Charge pump circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/234379 | Charge pump circuit | Sep 25, 2005 | Abandoned |
Array
(
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[patent_title] => 'Clock generators'
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[firstpage_image] =>[orig_patent_app_number] => 11232949
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232949 | Programmable fractional-N clock generators | Sep 22, 2005 | Issued |
Array
(
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[patent_title] => 'Matched current delay cell and delay locked loop'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232840 | Matched current delay cell and delay locked loop | Sep 20, 2005 | Issued |
Array
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Array
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