
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5724616
[patent_doc_number] => 20060055376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Input and output circuit and method of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 11/226564
[patent_app_country] => US
[patent_app_date] => 2005-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4950
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20060055376.pdf
[firstpage_image] =>[orig_patent_app_number] => 11226564
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226564 | Input and output circuit and method of operation thereof | Sep 13, 2005 | Issued |
Array
(
[id] => 537916
[patent_doc_number] => 07180343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Apparatus for synchronizing clock using source synchronous clock in optical transmission system'
[patent_app_type] => utility
[patent_app_number] => 11/223277
[patent_app_country] => US
[patent_app_date] => 2005-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3886
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/180/07180343.pdf
[firstpage_image] =>[orig_patent_app_number] => 11223277
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/223277 | Apparatus for synchronizing clock using source synchronous clock in optical transmission system | Sep 8, 2005 | Issued |
Array
(
[id] => 5589150
[patent_doc_number] => 20060038601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-23
[patent_title] => 'Clock signal generators having programmable full-period clock skew control'
[patent_app_type] => utility
[patent_app_number] => 11/217195
[patent_app_country] => US
[patent_app_date] => 2005-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5364
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20060038601.pdf
[firstpage_image] =>[orig_patent_app_number] => 11217195
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/217195 | Clock signal generators having programmable full-period clock skew control | Aug 31, 2005 | Issued |
Array
(
[id] => 465890
[patent_doc_number] => 07239189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Clock generating circuit'
[patent_app_type] => utility
[patent_app_number] => 11/206142
[patent_app_country] => US
[patent_app_date] => 2005-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7351
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/239/07239189.pdf
[firstpage_image] =>[orig_patent_app_number] => 11206142
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/206142 | Clock generating circuit | Aug 17, 2005 | Issued |
Array
(
[id] => 634992
[patent_doc_number] => 07129760
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Timing vernier using a delay locked loop'
[patent_app_type] => utility
[patent_app_number] => 11/205082
[patent_app_country] => US
[patent_app_date] => 2005-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6260
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/129/07129760.pdf
[firstpage_image] =>[orig_patent_app_number] => 11205082
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205082 | Timing vernier using a delay locked loop | Aug 16, 2005 | Issued |
Array
(
[id] => 436384
[patent_doc_number] => 07262642
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-28
[patent_title] => 'Semiconductor integrated circuit comprising first and second transmission systems'
[patent_app_type] => utility
[patent_app_number] => 11/203980
[patent_app_country] => US
[patent_app_date] => 2005-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 12952
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/262/07262642.pdf
[firstpage_image] =>[orig_patent_app_number] => 11203980
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/203980 | Semiconductor integrated circuit comprising first and second transmission systems | Aug 15, 2005 | Issued |
Array
(
[id] => 7603008
[patent_doc_number] => 07236026
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-26
[patent_title] => 'Circuit for and method of generating a frequency aligned clock signal'
[patent_app_type] => utility
[patent_app_number] => 11/169461
[patent_app_country] => US
[patent_app_date] => 2005-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4395
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/236/07236026.pdf
[firstpage_image] =>[orig_patent_app_number] => 11169461
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/169461 | Circuit for and method of generating a frequency aligned clock signal | Jun 28, 2005 | Issued |
Array
(
[id] => 532292
[patent_doc_number] => 07183830
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Integrated circuit and method for generating a clock signal'
[patent_app_type] => utility
[patent_app_number] => 11/168659
[patent_app_country] => US
[patent_app_date] => 2005-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4227
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/183/07183830.pdf
[firstpage_image] =>[orig_patent_app_number] => 11168659
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/168659 | Integrated circuit and method for generating a clock signal | Jun 27, 2005 | Issued |
Array
(
[id] => 470093
[patent_doc_number] => 07233182
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-19
[patent_title] => 'Circuitry for eliminating false lock in delay-locked loops'
[patent_app_type] => utility
[patent_app_number] => 11/169957
[patent_app_country] => US
[patent_app_date] => 2005-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4586
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/233/07233182.pdf
[firstpage_image] =>[orig_patent_app_number] => 11169957
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/169957 | Circuitry for eliminating false lock in delay-locked loops | Jun 27, 2005 | Issued |
Array
(
[id] => 5600046
[patent_doc_number] => 20060290391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-28
[patent_title] => 'Integrated clock generator with programmable spread spectrum using standard PLL circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/167629
[patent_app_country] => US
[patent_app_date] => 2005-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2078
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20060290391.pdf
[firstpage_image] =>[orig_patent_app_number] => 11167629
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/167629 | Integrated clock generator with programmable spread spectrum using standard PLL circuitry | Jun 26, 2005 | Issued |
Array
(
[id] => 444170
[patent_doc_number] => 07256646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-14
[patent_title] => 'Neutralization techniques for differential low noise amplifiers'
[patent_app_type] => utility
[patent_app_number] => 11/157246
[patent_app_country] => US
[patent_app_date] => 2005-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 7502
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/256/07256646.pdf
[firstpage_image] =>[orig_patent_app_number] => 11157246
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/157246 | Neutralization techniques for differential low noise amplifiers | Jun 20, 2005 | Issued |
Array
(
[id] => 6975934
[patent_doc_number] => 20050285649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Duty cycle correction circuit for use in a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/147629
[patent_app_country] => US
[patent_app_date] => 2005-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3122
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20050285649.pdf
[firstpage_image] =>[orig_patent_app_number] => 11147629
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/147629 | Duty cycle correction circuit for use in a semiconductor device | Jun 7, 2005 | Issued |
Array
(
[id] => 7054266
[patent_doc_number] => 20050275438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Capacitance multiplier with enhanced gain and low power consumption'
[patent_app_type] => utility
[patent_app_number] => 11/145254
[patent_app_country] => US
[patent_app_date] => 2005-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3905
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0275/20050275438.pdf
[firstpage_image] =>[orig_patent_app_number] => 11145254
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/145254 | Capacitance multiplier with enhanced gain and low power consumption | Jun 2, 2005 | Issued |
Array
(
[id] => 5629272
[patent_doc_number] => 20060145740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'VCDL-based dual loop DLL having infinite phase shift function'
[patent_app_type] => utility
[patent_app_number] => 11/142698
[patent_app_country] => US
[patent_app_date] => 2005-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6945
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20060145740.pdf
[firstpage_image] =>[orig_patent_app_number] => 11142698
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/142698 | VCDL-based dual loop DLL having infinite phase shift function | May 31, 2005 | Issued |
Array
(
[id] => 504420
[patent_doc_number] => 07205813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Differential type delay cells and methods of operating the same'
[patent_app_type] => utility
[patent_app_number] => 11/141568
[patent_app_country] => US
[patent_app_date] => 2005-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4687
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205813.pdf
[firstpage_image] =>[orig_patent_app_number] => 11141568
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/141568 | Differential type delay cells and methods of operating the same | May 30, 2005 | Issued |
Array
(
[id] => 5606129
[patent_doc_number] => 20060267645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'System and method for reducing transient response in a fractional N phase lock loop'
[patent_app_type] => utility
[patent_app_number] => 11/139160
[patent_app_country] => US
[patent_app_date] => 2005-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2094
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20060267645.pdf
[firstpage_image] =>[orig_patent_app_number] => 11139160
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/139160 | System and method for reducing transient response in a fractional N phase lock loop | May 27, 2005 | Issued |
Array
(
[id] => 683271
[patent_doc_number] => 07081782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-25
[patent_title] => 'Locked loop with dual rail regulation'
[patent_app_type] => utility
[patent_app_number] => 11/130682
[patent_app_country] => US
[patent_app_date] => 2005-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 29
[patent_no_of_words] => 17594
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/081/07081782.pdf
[firstpage_image] =>[orig_patent_app_number] => 11130682
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/130682 | Locked loop with dual rail regulation | May 16, 2005 | Issued |
Array
(
[id] => 696666
[patent_doc_number] => 07071743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-04
[patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 11/130079
[patent_app_country] => US
[patent_app_date] => 2005-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4218
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/071/07071743.pdf
[firstpage_image] =>[orig_patent_app_number] => 11130079
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/130079 | Programmable phase-locked loop circuitry for programmable logic device | May 15, 2005 | Issued |
Array
(
[id] => 401840
[patent_doc_number] => 07292077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-06
[patent_title] => 'Phase-lock loop and loop filter thereof'
[patent_app_type] => utility
[patent_app_number] => 11/122657
[patent_app_country] => US
[patent_app_date] => 2005-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3585
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/292/07292077.pdf
[firstpage_image] =>[orig_patent_app_number] => 11122657
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/122657 | Phase-lock loop and loop filter thereof | May 3, 2005 | Issued |
Array
(
[id] => 7177824
[patent_doc_number] => 20050189971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'System with dual rail regulated locked loop'
[patent_app_type] => utility
[patent_app_number] => 11/114433
[patent_app_country] => US
[patent_app_date] => 2005-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 31374
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20050189971.pdf
[firstpage_image] =>[orig_patent_app_number] => 11114433
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/114433 | System with dual rail regulated locked loop | Apr 25, 2005 | Issued |