Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 422302 [patent_doc_number] => 07274236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Variable delay line with multiple hierarchy' [patent_app_type] => utility [patent_app_number] => 11/107587 [patent_app_country] => US [patent_app_date] => 2005-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3401 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274236.pdf [firstpage_image] =>[orig_patent_app_number] => 11107587 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/107587
Variable delay line with multiple hierarchy Apr 14, 2005 Issued
Array ( [id] => 5854948 [patent_doc_number] => 20060226881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Sampling phase detector for delay-locked loop' [patent_app_type] => utility [patent_app_number] => 11/103527 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226881.pdf [firstpage_image] =>[orig_patent_app_number] => 11103527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103527
Sampling phase detector for delay-locked loop Apr 11, 2005 Issued
Array ( [id] => 5751572 [patent_doc_number] => 20060220721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Clock delay compensation circuit' [patent_app_type] => utility [patent_app_number] => 11/098106 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220721.pdf [firstpage_image] =>[orig_patent_app_number] => 11098106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098106
Clock delay compensation circuit Apr 3, 2005 Issued
Array ( [id] => 488134 [patent_doc_number] => 07218164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Emitter switching driving network to control the storage time' [patent_app_type] => utility [patent_app_number] => 11/097442 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 6024 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218164.pdf [firstpage_image] =>[orig_patent_app_number] => 11097442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097442
Emitter switching driving network to control the storage time Mar 30, 2005 Issued
Array ( [id] => 5629274 [patent_doc_number] => 20060145742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Pulse-on-edge circuit' [patent_app_type] => utility [patent_app_number] => 11/095238 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145742.pdf [firstpage_image] =>[orig_patent_app_number] => 11095238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095238
Pulse-on-edge circuit Mar 29, 2005 Issued
Array ( [id] => 509136 [patent_doc_number] => 07202709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Waveform output device and drive device' [patent_app_type] => utility [patent_app_number] => 11/088894 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4111 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202709.pdf [firstpage_image] =>[orig_patent_app_number] => 11088894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088894
Waveform output device and drive device Mar 24, 2005 Issued
Array ( [id] => 5698022 [patent_doc_number] => 20060214706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Reduced phase noise frequency divider' [patent_app_type] => utility [patent_app_number] => 11/090525 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1308 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214706.pdf [firstpage_image] =>[orig_patent_app_number] => 11090525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/090525
Reduced phase noise frequency divider Mar 24, 2005 Abandoned
Array ( [id] => 474491 [patent_doc_number] => 07230467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Constant edge generation circuits and methods and systems using the same' [patent_app_type] => utility [patent_app_number] => 11/089145 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230467.pdf [firstpage_image] =>[orig_patent_app_number] => 11089145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089145
Constant edge generation circuits and methods and systems using the same Mar 23, 2005 Issued
Array ( [id] => 681517 [patent_doc_number] => 07084681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'PLL lock detection circuit using edge detection and a state machine' [patent_app_type] => utility [patent_app_number] => 11/088152 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4757 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084681.pdf [firstpage_image] =>[orig_patent_app_number] => 11088152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088152
PLL lock detection circuit using edge detection and a state machine Mar 22, 2005 Issued
Array ( [id] => 398258 [patent_doc_number] => 07295049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method and circuit for rapid alignment of signals' [patent_app_type] => utility [patent_app_number] => 11/088028 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295049.pdf [firstpage_image] =>[orig_patent_app_number] => 11088028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088028
Method and circuit for rapid alignment of signals Mar 21, 2005 Issued
Array ( [id] => 627513 [patent_doc_number] => 07135900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Phase locked loop with adaptive loop bandwidth' [patent_app_type] => utility [patent_app_number] => 11/082497 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13980 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135900.pdf [firstpage_image] =>[orig_patent_app_number] => 11082497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082497
Phase locked loop with adaptive loop bandwidth Mar 16, 2005 Issued
Array ( [id] => 7002979 [patent_doc_number] => 20050168292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Leakage compensation for capacitors in loop filters' [patent_app_type] => utility [patent_app_number] => 11/084438 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5241 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20050168292.pdf [firstpage_image] =>[orig_patent_app_number] => 11084438 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/084438
Leakage compensation for capacitors in loop filters Mar 16, 2005 Issued
Array ( [id] => 532224 [patent_doc_number] => 07183823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter' [patent_app_type] => utility [patent_app_number] => 11/080882 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2787 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183823.pdf [firstpage_image] =>[orig_patent_app_number] => 11080882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080882
Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter Mar 14, 2005 Issued
Array ( [id] => 638854 [patent_doc_number] => 07126401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device' [patent_app_type] => utility [patent_app_number] => 11/077374 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7006 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126401.pdf [firstpage_image] =>[orig_patent_app_number] => 11077374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077374
Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device Mar 10, 2005 Issued
Array ( [id] => 730859 [patent_doc_number] => 07042255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Programmable differential capacitance for equalization circuits' [patent_app_type] => utility [patent_app_number] => 11/075368 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4151 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042255.pdf [firstpage_image] =>[orig_patent_app_number] => 11075368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/075368
Programmable differential capacitance for equalization circuits Mar 7, 2005 Issued
Array ( [id] => 873794 [patent_doc_number] => 07362152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Apparatus and method for digital phase control of a pulse width modulation generator for microprocessor/DSP in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/071027 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362152.pdf [firstpage_image] =>[orig_patent_app_number] => 11071027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071027
Apparatus and method for digital phase control of a pulse width modulation generator for microprocessor/DSP in integrated circuits Mar 2, 2005 Issued
Array ( [id] => 7048945 [patent_doc_number] => 20050184832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Symmetric microwave filter and microwave integrated circuit merging the same' [patent_app_type] => utility [patent_app_number] => 11/064003 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14740 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184832.pdf [firstpage_image] =>[orig_patent_app_number] => 11064003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064003
Symmetric microwave filter and microwave integrated circuit merging the same Feb 23, 2005 Issued
Array ( [id] => 775120 [patent_doc_number] => 07002390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Delay matching for clock distribution in a logic circuit' [patent_app_type] => utility [patent_app_number] => 11/053167 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4376 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002390.pdf [firstpage_image] =>[orig_patent_app_number] => 11053167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053167
Delay matching for clock distribution in a logic circuit Feb 6, 2005 Issued
Array ( [id] => 735166 [patent_doc_number] => 07038517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Timing vernier using a delay locked loop' [patent_app_type] => utility [patent_app_number] => 11/037365 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038517.pdf [firstpage_image] =>[orig_patent_app_number] => 11037365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037365
Timing vernier using a delay locked loop Jan 18, 2005 Issued
Array ( [id] => 7169972 [patent_doc_number] => 20050122137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'High speed peak amplitude comparator' [patent_app_type] => utility [patent_app_number] => 11/031102 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122137.pdf [firstpage_image] =>[orig_patent_app_number] => 11031102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/031102
High speed peak amplitude comparator Jan 5, 2005 Issued
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