
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 785964
[patent_doc_number] => 06989697
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[patent_issue_date] => 2006-01-24
[patent_title] => 'Non-quasistatic phase lock loop frequency divider circuit'
[patent_app_type] => utility
[patent_app_number] => 11/030345
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Array
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[patent_issue_date] => 2006-07-06
[patent_title] => 'Signal processing apparatus having internal clock signal source'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/026654 | Signal processing apparatus having internal clock signal source | Dec 30, 2004 | Issued |
Array
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[patent_issue_date] => 2006-07-06
[patent_title] => 'Method and circuit configuration for synchronous resetting of a multiple clock domain circuit'
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[patent_app_number] => 11/027906
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Array
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[patent_title] => 'Z-state circuit for delay-locked loops'
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Array
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[patent_title] => 'Timing adjustment circuit and memory controller'
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Array
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Array
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Array
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[patent_title] => 'Delay locked loop in semiconductor memory device and locking method thereof'
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Array
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[id] => 540519
[patent_doc_number] => 07173459
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[patent_issue_date] => 2007-02-06
[patent_title] => 'Trimming method and apparatus for voltage controlled delay loop with central interpolator'
[patent_app_type] => utility
[patent_app_number] => 11/020022
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Array
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[patent_title] => 'Digital delay locked loop capable of correcting duty cycle and its method'
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[patent_app_number] => 11/020491
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Array
(
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[patent_title] => 'Dual-edge synchronized data sampler'
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Array
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Array
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Array
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Array
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Array
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Array
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