Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 785964 [patent_doc_number] => 06989697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Non-quasistatic phase lock loop frequency divider circuit' [patent_app_type] => utility [patent_app_number] => 11/030345 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6626 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989697.pdf [firstpage_image] =>[orig_patent_app_number] => 11030345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030345
Non-quasistatic phase lock loop frequency divider circuit Jan 5, 2005 Issued
Array ( [id] => 5629262 [patent_doc_number] => 20060145730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Signal processing apparatus having internal clock signal source' [patent_app_type] => utility [patent_app_number] => 11/026654 [patent_app_country] => US [patent_app_date] => 2004-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145730.pdf [firstpage_image] =>[orig_patent_app_number] => 11026654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026654
Signal processing apparatus having internal clock signal source Dec 30, 2004 Issued
Array ( [id] => 5629270 [patent_doc_number] => 20060145738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method and circuit configuration for synchronous resetting of a multiple clock domain circuit' [patent_app_type] => utility [patent_app_number] => 11/027906 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145738.pdf [firstpage_image] =>[orig_patent_app_number] => 11027906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027906
Method and circuit configuration for synchronous resetting of a multiple clock domain circuit Dec 29, 2004 Issued
Array ( [id] => 5653341 [patent_doc_number] => 20060139076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Z-state circuit for delay-locked loops' [patent_app_type] => utility [patent_app_number] => 11/024542 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139076.pdf [firstpage_image] =>[orig_patent_app_number] => 11024542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024542
Z-state circuit for delay-locked loops Dec 27, 2004 Abandoned
Array ( [id] => 394487 [patent_doc_number] => 07298188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Timing adjustment circuit and memory controller' [patent_app_type] => utility [patent_app_number] => 11/020418 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298188.pdf [firstpage_image] =>[orig_patent_app_number] => 11020418 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020418
Timing adjustment circuit and memory controller Dec 26, 2004 Issued
Array ( [id] => 613330 [patent_doc_number] => 07148730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Z-state circuit for phase-locked loops' [patent_app_type] => utility [patent_app_number] => 11/023683 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148730.pdf [firstpage_image] =>[orig_patent_app_number] => 11023683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/023683
Z-state circuit for phase-locked loops Dec 26, 2004 Issued
Array ( [id] => 5653340 [patent_doc_number] => 20060139075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Delay locked loop using synchronous mirror delay' [patent_app_type] => utility [patent_app_number] => 11/021370 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8766 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139075.pdf [firstpage_image] =>[orig_patent_app_number] => 11021370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021370
Delay locked loop using synchronous mirror delay Dec 22, 2004 Issued
Array ( [id] => 7239231 [patent_doc_number] => 20050140408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Delay locked loop in semiconductor memory device and locking method thereof' [patent_app_type] => utility [patent_app_number] => 11/017644 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1842 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140408.pdf [firstpage_image] =>[orig_patent_app_number] => 11017644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017644
Delay locked loop in semiconductor memory device and locking method thereof Dec 21, 2004 Issued
Array ( [id] => 540519 [patent_doc_number] => 07173459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Trimming method and apparatus for voltage controlled delay loop with central interpolator' [patent_app_type] => utility [patent_app_number] => 11/020022 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173459.pdf [firstpage_image] =>[orig_patent_app_number] => 11020022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020022
Trimming method and apparatus for voltage controlled delay loop with central interpolator Dec 21, 2004 Issued
Array ( [id] => 562551 [patent_doc_number] => 07161397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Digital delay locked loop capable of correcting duty cycle and its method' [patent_app_type] => utility [patent_app_number] => 11/020491 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4777 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161397.pdf [firstpage_image] =>[orig_patent_app_number] => 11020491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020491
Digital delay locked loop capable of correcting duty cycle and its method Dec 20, 2004 Issued
Array ( [id] => 523778 [patent_doc_number] => 07190196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-13 [patent_title] => 'Dual-edge synchronized data sampler' [patent_app_type] => utility [patent_app_number] => 11/015322 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5957 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190196.pdf [firstpage_image] =>[orig_patent_app_number] => 11015322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015322
Dual-edge synchronized data sampler Dec 16, 2004 Issued
Array ( [id] => 638850 [patent_doc_number] => 07126400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Delay adjustment circuit, integrated circuit device, and delay adjustment method' [patent_app_type] => utility [patent_app_number] => 11/013472 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126400.pdf [firstpage_image] =>[orig_patent_app_number] => 11013472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013472
Delay adjustment circuit, integrated circuit device, and delay adjustment method Dec 16, 2004 Issued
Array ( [id] => 624130 [patent_doc_number] => 07138841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'Programmable phase shift and duty cycle correction circuit and method' [patent_app_type] => utility [patent_app_number] => 11/014578 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7223 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138841.pdf [firstpage_image] =>[orig_patent_app_number] => 11014578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/014578
Programmable phase shift and duty cycle correction circuit and method Dec 15, 2004 Issued
Array ( [id] => 6994575 [patent_doc_number] => 20050134353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Semiconductor integrated circuit and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/012724 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4798 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134353.pdf [firstpage_image] =>[orig_patent_app_number] => 11012724 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012724
Semiconductor integrated circuit and manufacturing method Dec 15, 2004 Issued
Array ( [id] => 785980 [patent_doc_number] => 06989704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Delay circuit having function of filter circuit' [patent_app_type] => utility [patent_app_number] => 11/010290 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5254 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989704.pdf [firstpage_image] =>[orig_patent_app_number] => 11010290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010290
Delay circuit having function of filter circuit Dec 13, 2004 Issued
Array ( [id] => 542014 [patent_doc_number] => 07176733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'High output impedance charge pump for PLL/DLL' [patent_app_type] => utility [patent_app_number] => 11/009534 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5949 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176733.pdf [firstpage_image] =>[orig_patent_app_number] => 11009534 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009534
High output impedance charge pump for PLL/DLL Dec 9, 2004 Issued
Array ( [id] => 683274 [patent_doc_number] => 07081784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Data output circuit of memory device' [patent_app_type] => utility [patent_app_number] => 11/008254 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1752 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081784.pdf [firstpage_image] =>[orig_patent_app_number] => 11008254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008254
Data output circuit of memory device Dec 9, 2004 Issued
Array ( [id] => 5909831 [patent_doc_number] => 20060125534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Zero idle time Z-state circuit for phase-locked loops, delay-locked loops, and switching regulators' [patent_app_type] => utility [patent_app_number] => 11/009648 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125534.pdf [firstpage_image] =>[orig_patent_app_number] => 11009648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009648
Zero idle time Z-state circuit for phase-locked loops, delay-locked loops, and switching regulators Dec 8, 2004 Issued
Array ( [id] => 7172562 [patent_doc_number] => 20050122820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor devices including an external power voltage control function and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 11/005523 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9164 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122820.pdf [firstpage_image] =>[orig_patent_app_number] => 11005523 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005523
Semiconductor devices including an external power voltage control function and methods of operating the same Dec 5, 2004 Issued
Array ( [id] => 5838913 [patent_doc_number] => 20060119396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Skew tolerant high-speed digital phase detector' [patent_app_type] => utility [patent_app_number] => 11/003117 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3905 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119396.pdf [firstpage_image] =>[orig_patent_app_number] => 11003117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003117
Skew tolerant high-speed digital phase detector Dec 2, 2004 Issued
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