Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5838914 [patent_doc_number] => 20060119397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Apparatus and method for accurately tuning the speed of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/002548 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119397.pdf [firstpage_image] =>[orig_patent_app_number] => 11002548 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002548
Apparatus and method for accurately tuning the speed of an integrated circuit Dec 1, 2004 Issued
Array ( [id] => 634986 [patent_doc_number] => 07129757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Clock frequency detect with programmable jitter tolerance' [patent_app_type] => utility [patent_app_number] => 11/000439 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6443 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129757.pdf [firstpage_image] =>[orig_patent_app_number] => 11000439 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000439
Clock frequency detect with programmable jitter tolerance Nov 29, 2004 Issued
Array ( [id] => 5612119 [patent_doc_number] => 20060114045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Voltage controlled delay loop with central interpolator' [patent_app_type] => utility [patent_app_number] => 10/999889 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2488 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20060114045.pdf [firstpage_image] =>[orig_patent_app_number] => 10999889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999889
Voltage controlled delay loop with central interpolator Nov 29, 2004 Issued
Array ( [id] => 6994565 [patent_doc_number] => 20050134343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'PWM signal generator' [patent_app_type] => utility [patent_app_number] => 10/998992 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4238 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134343.pdf [firstpage_image] =>[orig_patent_app_number] => 10998992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998992
PWM signal generator Nov 29, 2004 Issued
Array ( [id] => 638832 [patent_doc_number] => 07126392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Semiconductor integrated device having reduced jitter and reduced current consumption' [patent_app_type] => utility [patent_app_number] => 10/999365 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5255 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126392.pdf [firstpage_image] =>[orig_patent_app_number] => 10999365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999365
Semiconductor integrated device having reduced jitter and reduced current consumption Nov 28, 2004 Issued
Array ( [id] => 477168 [patent_doc_number] => 07227393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters' [patent_app_type] => utility [patent_app_number] => 10/997236 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3854 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227393.pdf [firstpage_image] =>[orig_patent_app_number] => 10997236 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997236
Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters Nov 23, 2004 Issued
Array ( [id] => 549859 [patent_doc_number] => 07164303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Delay circuit, ferroelectric memory device and electronic equipment' [patent_app_type] => utility [patent_app_number] => 10/997820 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5340 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164303.pdf [firstpage_image] =>[orig_patent_app_number] => 10997820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997820
Delay circuit, ferroelectric memory device and electronic equipment Nov 23, 2004 Issued
Array ( [id] => 6956254 [patent_doc_number] => 20050212624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Microwave circuit' [patent_app_type] => utility [patent_app_number] => 10/988152 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1641 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212624.pdf [firstpage_image] =>[orig_patent_app_number] => 10988152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988152
Microwave circuit Nov 11, 2004 Issued
Array ( [id] => 504377 [patent_doc_number] => 07205805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error' [patent_app_type] => utility [patent_app_number] => 10/980676 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5026 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205805.pdf [firstpage_image] =>[orig_patent_app_number] => 10980676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980676
Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error Nov 1, 2004 Issued
Array ( [id] => 6916038 [patent_doc_number] => 20050093599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Delayed locked loops and methods of driving the same' [patent_app_type] => utility [patent_app_number] => 10/978623 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2687 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093599.pdf [firstpage_image] =>[orig_patent_app_number] => 10978623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978623
Delayed locked loops and methods of driving the same Oct 31, 2004 Issued
Array ( [id] => 709124 [patent_doc_number] => 07061277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Low power differential-to-single-ended converter with good duty cycle performance' [patent_app_type] => utility [patent_app_number] => 10/972744 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061277.pdf [firstpage_image] =>[orig_patent_app_number] => 10972744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/972744
Low power differential-to-single-ended converter with good duty cycle performance Oct 24, 2004 Issued
Array ( [id] => 541940 [patent_doc_number] => 07176726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Integrated loss of signal detection with wide threshold range and precise hysteresis' [patent_app_type] => utility [patent_app_number] => 10/967037 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1657 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176726.pdf [firstpage_image] =>[orig_patent_app_number] => 10967037 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/967037
Integrated loss of signal detection with wide threshold range and precise hysteresis Oct 14, 2004 Issued
Array ( [id] => 504432 [patent_doc_number] => 07205815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Method and integrated circuit apparatus for reducing simultaneously switching output' [patent_app_type] => utility [patent_app_number] => 10/963532 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205815.pdf [firstpage_image] =>[orig_patent_app_number] => 10963532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/963532
Method and integrated circuit apparatus for reducing simultaneously switching output Oct 13, 2004 Issued
Array ( [id] => 5713630 [patent_doc_number] => 20060076993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'High speed clock and data recovery system' [patent_app_type] => utility [patent_app_number] => 10/961201 [patent_app_country] => US [patent_app_date] => 2004-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7935 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076993.pdf [firstpage_image] =>[orig_patent_app_number] => 10961201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/961201
High speed clock and data recovery system Oct 11, 2004 Issued
Array ( [id] => 7607010 [patent_doc_number] => 07098706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops' [patent_app_type] => utility [patent_app_number] => 10/959573 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 42 [patent_no_of_words] => 5378 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098706.pdf [firstpage_image] =>[orig_patent_app_number] => 10959573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959573
High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops Oct 5, 2004 Issued
Array ( [id] => 7222591 [patent_doc_number] => 20050077943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/958466 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8019 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077943.pdf [firstpage_image] =>[orig_patent_app_number] => 10958466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/958466
Semiconductor integrated circuit Oct 5, 2004 Issued
Array ( [id] => 7243977 [patent_doc_number] => 20050073343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof' [patent_app_type] => utility [patent_app_number] => 10/960367 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7800 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073343.pdf [firstpage_image] =>[orig_patent_app_number] => 10960367 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/960367
Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof Oct 5, 2004 Issued
Array ( [id] => 656221 [patent_doc_number] => 07109773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Flexible blender' [patent_app_type] => utility [patent_app_number] => 10/957803 [patent_app_country] => US [patent_app_date] => 2004-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109773.pdf [firstpage_image] =>[orig_patent_app_number] => 10957803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957803
Flexible blender Oct 3, 2004 Issued
Array ( [id] => 643175 [patent_doc_number] => 07123064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Digital phase shift circuits' [patent_app_type] => utility [patent_app_number] => 10/956848 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11411 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123064.pdf [firstpage_image] =>[orig_patent_app_number] => 10956848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956848
Digital phase shift circuits Sep 30, 2004 Issued
Array ( [id] => 613328 [patent_doc_number] => 07148728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Digital delay device, digital oscillator clock signal generator and memory interface' [patent_app_type] => utility [patent_app_number] => 10/957211 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6453 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148728.pdf [firstpage_image] =>[orig_patent_app_number] => 10957211 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957211
Digital delay device, digital oscillator clock signal generator and memory interface Sep 30, 2004 Issued
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