Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 627510 [patent_doc_number] => 07135897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Clock resynchronizer' [patent_app_type] => utility [patent_app_number] => 10/944938 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10488 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135897.pdf [firstpage_image] =>[orig_patent_app_number] => 10944938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944938
Clock resynchronizer Sep 20, 2004 Issued
Array ( [id] => 7193158 [patent_doc_number] => 20050040891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'System and method for a programmable gain amplifier' [patent_app_type] => utility [patent_app_number] => 10/944007 [patent_app_country] => US [patent_app_date] => 2004-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5442 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040891.pdf [firstpage_image] =>[orig_patent_app_number] => 10944007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944007
System and method for a programmable gain amplifier Sep 19, 2004 Issued
Array ( [id] => 935799 [patent_doc_number] => 06975149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method and circuit for adjusting the timing of output data based on an operational mode of output drivers' [patent_app_type] => utility [patent_app_number] => 10/944136 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8469 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975149.pdf [firstpage_image] =>[orig_patent_app_number] => 10944136 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944136
Method and circuit for adjusting the timing of output data based on an operational mode of output drivers Sep 15, 2004 Issued
Array ( [id] => 979522 [patent_doc_number] => 06930528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Delay circuit and method with delay relatively independent of process, voltage, and temperature variations' [patent_app_type] => utility [patent_app_number] => 10/938956 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4656 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930528.pdf [firstpage_image] =>[orig_patent_app_number] => 10938956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/938956
Delay circuit and method with delay relatively independent of process, voltage, and temperature variations Sep 12, 2004 Issued
Array ( [id] => 646739 [patent_doc_number] => 07119589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof' [patent_app_type] => utility [patent_app_number] => 10/711313 [patent_app_country] => US [patent_app_date] => 2004-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119589.pdf [firstpage_image] =>[orig_patent_app_number] => 10711313 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711313
Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof Sep 9, 2004 Issued
Array ( [id] => 681523 [patent_doc_number] => 07084685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and related apparatus for outputting clock through a data path' [patent_app_type] => utility [patent_app_number] => 10/711254 [patent_app_country] => US [patent_app_date] => 2004-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8702 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084685.pdf [firstpage_image] =>[orig_patent_app_number] => 10711254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711254
Method and related apparatus for outputting clock through a data path Sep 3, 2004 Issued
Array ( [id] => 739783 [patent_doc_number] => 07034597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Dynamic phase alignment of a clock and data signal using an adjustable clock delay line' [patent_app_type] => utility [patent_app_number] => 10/933742 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4381 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034597.pdf [firstpage_image] =>[orig_patent_app_number] => 10933742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/933742
Dynamic phase alignment of a clock and data signal using an adjustable clock delay line Sep 2, 2004 Issued
Array ( [id] => 7031571 [patent_doc_number] => 20050030080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method and circuitry for reducing duty cycle distortion in differential delay lines' [patent_app_type] => utility [patent_app_number] => 10/932668 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2723 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030080.pdf [firstpage_image] =>[orig_patent_app_number] => 10932668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932668
Method and circuitry for reducing duty cycle distortion in differential delay lines Aug 31, 2004 Issued
Array ( [id] => 743621 [patent_doc_number] => 07030675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Apparatus and method for controlling a delay chain' [patent_app_type] => utility [patent_app_number] => 10/932642 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030675.pdf [firstpage_image] =>[orig_patent_app_number] => 10932642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932642
Apparatus and method for controlling a delay chain Aug 30, 2004 Issued
Array ( [id] => 5899023 [patent_doc_number] => 20060044026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method and apparatus for timing domain crossing' [patent_app_type] => utility [patent_app_number] => 10/931397 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6921 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044026.pdf [firstpage_image] =>[orig_patent_app_number] => 10931397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931397
Method and apparatus for timing domain crossing Aug 30, 2004 Issued
Array ( [id] => 7196214 [patent_doc_number] => 20050041486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Delay locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/931843 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4096 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041486.pdf [firstpage_image] =>[orig_patent_app_number] => 10931843 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931843
Delay locked loop circuit with time delay quantifier and control Aug 30, 2004 Issued
Array ( [id] => 681529 [patent_doc_number] => 07084688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Clock distribution providing optimal delay' [patent_app_type] => utility [patent_app_number] => 10/929630 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2255 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084688.pdf [firstpage_image] =>[orig_patent_app_number] => 10929630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929630
Clock distribution providing optimal delay Aug 29, 2004 Issued
Array ( [id] => 664469 [patent_doc_number] => 07102400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Phase locked loop charge pump and method of operation' [patent_app_type] => utility [patent_app_number] => 10/929158 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4989 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102400.pdf [firstpage_image] =>[orig_patent_app_number] => 10929158 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929158
Phase locked loop charge pump and method of operation Aug 29, 2004 Issued
Array ( [id] => 5899018 [patent_doc_number] => 20060044021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'FALSE-LOCK-FREE DELAY LOCKED LOOP CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 10/929180 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8811 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044021.pdf [firstpage_image] =>[orig_patent_app_number] => 10929180 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929180
False-lock-free delay locked loop circuit and method Aug 29, 2004 Issued
Array ( [id] => 688127 [patent_doc_number] => 07078951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 10/928424 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6408 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078951.pdf [firstpage_image] =>[orig_patent_app_number] => 10928424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928424
System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Aug 26, 2004 Issued
Array ( [id] => 730882 [patent_doc_number] => 07042265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Interlaced delay-locked loops for controlling memory-circuit timing' [patent_app_type] => utility [patent_app_number] => 10/914757 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4716 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042265.pdf [firstpage_image] =>[orig_patent_app_number] => 10914757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914757
Interlaced delay-locked loops for controlling memory-circuit timing Aug 8, 2004 Issued
Array ( [id] => 646732 [patent_doc_number] => 07119582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Phase detection in a sync pulse generator' [patent_app_type] => utility [patent_app_number] => 10/898693 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9485 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119582.pdf [firstpage_image] =>[orig_patent_app_number] => 10898693 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898693
Phase detection in a sync pulse generator Jul 22, 2004 Issued
Array ( [id] => 775108 [patent_doc_number] => 07002382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/895080 [patent_app_country] => US [patent_app_date] => 2004-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4677 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002382.pdf [firstpage_image] =>[orig_patent_app_number] => 10895080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895080
Phase locked loop circuit Jul 20, 2004 Issued
Array ( [id] => 5763555 [patent_doc_number] => 20060017479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'METHOD AND APPARATUS FOR DIGITAL PHASE GENERATION AT HIGH FREQUENCIES' [patent_app_type] => utility [patent_app_number] => 10/896159 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7798 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20060017479.pdf [firstpage_image] =>[orig_patent_app_number] => 10896159 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/896159
Method and apparatus for digital phase generation at high frequencies Jul 19, 2004 Issued
Array ( [id] => 688126 [patent_doc_number] => 07078950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Delay-locked loop with feedback compensation' [patent_app_type] => utility [patent_app_number] => 10/895649 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3891 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078950.pdf [firstpage_image] =>[orig_patent_app_number] => 10895649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895649
Delay-locked loop with feedback compensation Jul 19, 2004 Issued
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