Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 726402 [patent_doc_number] => 07046069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method to reduce inductive effects of current variations by internal clock phase shifting' [patent_app_type] => utility [patent_app_number] => 10/894148 [patent_app_country] => US [patent_app_date] => 2004-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2508 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046069.pdf [firstpage_image] =>[orig_patent_app_number] => 10894148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894148
Method to reduce inductive effects of current variations by internal clock phase shifting Jul 18, 2004 Issued
Array ( [id] => 7200596 [patent_doc_number] => 20050052252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Synchronizing unit for redundant system clocks' [patent_app_type] => utility [patent_app_number] => 10/891886 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7118 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052252.pdf [firstpage_image] =>[orig_patent_app_number] => 10891886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891886
Synchronizing unit for redundant system clocks Jul 14, 2004 Abandoned
Array ( [id] => 5736525 [patent_doc_number] => 20060006915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Signal slew rate control for image sensors' [patent_app_type] => utility [patent_app_number] => 10/887891 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4737 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006915.pdf [firstpage_image] =>[orig_patent_app_number] => 10887891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887891
Signal slew rate control for image sensors Jul 11, 2004 Abandoned
Array ( [id] => 656215 [patent_doc_number] => 07109767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Generating different delay ratios for a strobe delay' [patent_app_type] => utility [patent_app_number] => 10/889610 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2990 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109767.pdf [firstpage_image] =>[orig_patent_app_number] => 10889610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889610
Generating different delay ratios for a strobe delay Jul 11, 2004 Issued
Array ( [id] => 762628 [patent_doc_number] => 07012472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Digital control loop to improve phase noise performance and RX/TX linearity' [patent_app_type] => utility [patent_app_number] => 10/888861 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 5290 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012472.pdf [firstpage_image] =>[orig_patent_app_number] => 10888861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/888861
Digital control loop to improve phase noise performance and RX/TX linearity Jul 8, 2004 Issued
Array ( [id] => 756980 [patent_doc_number] => 07019569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Method of implementing multi-transfer curve phase lock loop' [patent_app_type] => utility [patent_app_number] => 10/888878 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2182 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019569.pdf [firstpage_image] =>[orig_patent_app_number] => 10888878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/888878
Method of implementing multi-transfer curve phase lock loop Jul 8, 2004 Issued
Array ( [id] => 5893959 [patent_doc_number] => 20060002497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'PHASE ADJUSTMENT METHOD AND CIRCUIT FOR DLL-BASED SERIAL DATA LINK TRANSCEIVERS' [patent_app_type] => utility [patent_app_number] => 10/882428 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2949 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002497.pdf [firstpage_image] =>[orig_patent_app_number] => 10882428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882428
Phase adjustment method and circuit for DLL-based serial data link transceivers Jul 1, 2004 Issued
Array ( [id] => 7609303 [patent_doc_number] => 06998886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Apparatus and method for PLL with equalizing pulse removal' [patent_app_type] => utility [patent_app_number] => 10/881483 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998886.pdf [firstpage_image] =>[orig_patent_app_number] => 10881483 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881483
Apparatus and method for PLL with equalizing pulse removal Jun 29, 2004 Issued
Array ( [id] => 664467 [patent_doc_number] => 07102398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Circuit for two PLLs for horizontal deflection' [patent_app_type] => utility [patent_app_number] => 10/880954 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8046 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102398.pdf [firstpage_image] =>[orig_patent_app_number] => 10880954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880954
Circuit for two PLLs for horizontal deflection Jun 29, 2004 Issued
Array ( [id] => 703660 [patent_doc_number] => 07064617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method and apparatus for temperature compensation' [patent_app_type] => utility [patent_app_number] => 10/878196 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10491 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064617.pdf [firstpage_image] =>[orig_patent_app_number] => 10878196 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878196
Method and apparatus for temperature compensation Jun 27, 2004 Issued
Array ( [id] => 412179 [patent_doc_number] => 07282976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Apparatus and method for duty cycle correction' [patent_app_type] => utility [patent_app_number] => 10/876209 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2297 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282976.pdf [firstpage_image] =>[orig_patent_app_number] => 10876209 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876209
Apparatus and method for duty cycle correction Jun 22, 2004 Issued
Array ( [id] => 7149032 [patent_doc_number] => 20050024106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Charge pump system for fast locking phase lock loop' [patent_app_type] => utility [patent_app_number] => 10/874641 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5153 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024106.pdf [firstpage_image] =>[orig_patent_app_number] => 10874641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874641
Charge pump system for fast locking phase lock loop Jun 22, 2004 Issued
Array ( [id] => 1006394 [patent_doc_number] => 06906565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Fast lock phase lock loop and method thereof' [patent_app_type] => utility [patent_app_number] => 10/874646 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5645 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906565.pdf [firstpage_image] =>[orig_patent_app_number] => 10874646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874646
Fast lock phase lock loop and method thereof Jun 22, 2004 Issued
Array ( [id] => 630911 [patent_doc_number] => 07132872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Apparatus and method for generating a phase delay' [patent_app_type] => utility [patent_app_number] => 10/710175 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1885 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132872.pdf [firstpage_image] =>[orig_patent_app_number] => 10710175 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710175
Apparatus and method for generating a phase delay Jun 22, 2004 Issued
Array ( [id] => 7149041 [patent_doc_number] => 20050024112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Pulse width modulated common mode feedback loop and method for differential charge pump' [patent_app_type] => utility [patent_app_number] => 10/873318 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3898 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024112.pdf [firstpage_image] =>[orig_patent_app_number] => 10873318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/873318
Pulse width modulated common mode feedback loop and method for differential charge pump Jun 21, 2004 Issued
Array ( [id] => 651433 [patent_doc_number] => 07113011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Low power PLL for PWM switching digital control power supply' [patent_app_type] => utility [patent_app_number] => 10/872702 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6809 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113011.pdf [firstpage_image] =>[orig_patent_app_number] => 10872702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/872702
Low power PLL for PWM switching digital control power supply Jun 20, 2004 Issued
Array ( [id] => 721773 [patent_doc_number] => 07049864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Apparatus and method for high frequency state machine divider with low power consumption' [patent_app_type] => utility [patent_app_number] => 10/710115 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5485 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049864.pdf [firstpage_image] =>[orig_patent_app_number] => 10710115 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710115
Apparatus and method for high frequency state machine divider with low power consumption Jun 17, 2004 Issued
Array ( [id] => 726396 [patent_doc_number] => 07046066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method and/or apparatus for generating a write gated clock signal' [patent_app_type] => utility [patent_app_number] => 10/867899 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046066.pdf [firstpage_image] =>[orig_patent_app_number] => 10867899 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867899
Method and/or apparatus for generating a write gated clock signal Jun 14, 2004 Issued
Array ( [id] => 7239208 [patent_doc_number] => 20050140402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Frequency converter' [patent_app_type] => utility [patent_app_number] => 10/866458 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3625 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140402.pdf [firstpage_image] =>[orig_patent_app_number] => 10866458 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866458
Frequency converter Jun 9, 2004 Abandoned
Array ( [id] => 7023384 [patent_doc_number] => 20050017778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Pulse signal generator and display device' [patent_app_type] => utility [patent_app_number] => 10/863184 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017778.pdf [firstpage_image] =>[orig_patent_app_number] => 10863184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863184
Pulse signal generator and display device Jun 6, 2004 Issued
Menu