Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 638845 [patent_doc_number] => 07126399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Memory interface phase-shift circuitry to support multiple frequency ranges' [patent_app_type] => utility [patent_app_number] => 10/857221 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8648 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126399.pdf [firstpage_image] =>[orig_patent_app_number] => 10857221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/857221
Memory interface phase-shift circuitry to support multiple frequency ranges May 26, 2004 Issued
Array ( [id] => 6942964 [patent_doc_number] => 20050195012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/853260 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195012.pdf [firstpage_image] =>[orig_patent_app_number] => 10853260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853260
Semiconductor device to prevent a circuit from being inadvertently active May 25, 2004 Issued
Array ( [id] => 7364574 [patent_doc_number] => 20040217781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Diode multiplexer circuit and electronic device incorporating the same' [patent_app_type] => new [patent_app_number] => 10/853350 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5475 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217781.pdf [firstpage_image] =>[orig_patent_app_number] => 10853350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853350
Diode multiplexer circuit and electronic device incorporating the same May 24, 2004 Abandoned
Array ( [id] => 681526 [patent_doc_number] => 07084686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 10/854849 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 5824 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084686.pdf [firstpage_image] =>[orig_patent_app_number] => 10854849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854849
System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal May 24, 2004 Issued
Array ( [id] => 7059303 [patent_doc_number] => 20050001662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'System with phase jumping locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/852650 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 26859 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001662.pdf [firstpage_image] =>[orig_patent_app_number] => 10852650 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/852650
System with phase jumping locked loop circuit May 23, 2004 Issued
Array ( [id] => 7292408 [patent_doc_number] => 20040212411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => new [patent_app_number] => 10/851891 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14397 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212411.pdf [firstpage_image] =>[orig_patent_app_number] => 10851891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851891
Clock controlling method and circuit May 20, 2004 Issued
Array ( [id] => 739760 [patent_doc_number] => 07034592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => utility [patent_app_number] => 10/851905 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14294 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034592.pdf [firstpage_image] =>[orig_patent_app_number] => 10851905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851905
Clock controlling method and circuit May 20, 2004 Issued
Array ( [id] => 1009916 [patent_doc_number] => 06900680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => utility [patent_app_number] => 10/851272 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14312 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900680.pdf [firstpage_image] =>[orig_patent_app_number] => 10851272 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851272
Clock controlling method and circuit May 20, 2004 Issued
Array ( [id] => 7364593 [patent_doc_number] => 20040217786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => new [patent_app_number] => 10/851271 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14397 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217786.pdf [firstpage_image] =>[orig_patent_app_number] => 10851271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851271
Clock controlling method and circuit May 20, 2004 Issued
Array ( [id] => 5713631 [patent_doc_number] => 20060076994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Pulse generator' [patent_app_type] => utility [patent_app_number] => 10/543534 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13415 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076994.pdf [firstpage_image] =>[orig_patent_app_number] => 10543534 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/543534
Pulse generator May 18, 2004 Issued
Array ( [id] => 7012610 [patent_doc_number] => 20050065745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device' [patent_app_type] => utility [patent_app_number] => 10/845356 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4376 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20050065745.pdf [firstpage_image] =>[orig_patent_app_number] => 10845356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845356
Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device May 13, 2004 Issued
Array ( [id] => 7414410 [patent_doc_number] => 20040207436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Timing generating apparatus and test apparatus' [patent_app_type] => new [patent_app_number] => 10/844248 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207436.pdf [firstpage_image] =>[orig_patent_app_number] => 10844248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844248
Timing generating apparatus and test apparatus May 11, 2004 Issued
Array ( [id] => 7273548 [patent_doc_number] => 20040232999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Section selection loop filter and phase locked loop circuit having the same' [patent_app_type] => new [patent_app_number] => 10/840491 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5162 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232999.pdf [firstpage_image] =>[orig_patent_app_number] => 10840491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840491
Section selection loop filter and phase locked loop circuit having the same May 5, 2004 Issued
Array ( [id] => 938775 [patent_doc_number] => 06972604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Circuit for compensating LPF capacitor charge leakage in phase locked loop systems' [patent_app_type] => utility [patent_app_number] => 10/840562 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972604.pdf [firstpage_image] =>[orig_patent_app_number] => 10840562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840562
Circuit for compensating LPF capacitor charge leakage in phase locked loop systems May 5, 2004 Issued
Array ( [id] => 770685 [patent_doc_number] => 07005904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Duty cycle correction' [patent_app_type] => utility [patent_app_number] => 10/836754 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/005/07005904.pdf [firstpage_image] =>[orig_patent_app_number] => 10836754 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836754
Duty cycle correction Apr 29, 2004 Issued
Array ( [id] => 7222550 [patent_doc_number] => 20050077937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Current starved DAC-controlled delay locked loop' [patent_app_type] => utility [patent_app_number] => 10/836704 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2400 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077937.pdf [firstpage_image] =>[orig_patent_app_number] => 10836704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836704
Current starved DAC-controlled delay locked loop Apr 28, 2004 Issued
Array ( [id] => 474548 [patent_doc_number] => 07230495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Phase-locked loop circuits with reduced lock time' [patent_app_type] => utility [patent_app_number] => 10/834775 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4486 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230495.pdf [firstpage_image] =>[orig_patent_app_number] => 10834775 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834775
Phase-locked loop circuits with reduced lock time Apr 27, 2004 Issued
Array ( [id] => 7149008 [patent_doc_number] => 20050024094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Rotational frequency detector system' [patent_app_type] => utility [patent_app_number] => 10/830664 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6701 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024094.pdf [firstpage_image] =>[orig_patent_app_number] => 10830664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830664
Rotational frequency detector system Apr 22, 2004 Issued
Array ( [id] => 793527 [patent_doc_number] => 06982573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Switchable clock source' [patent_app_type] => utility [patent_app_number] => 10/827675 [patent_app_country] => US [patent_app_date] => 2004-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4621 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982573.pdf [firstpage_image] =>[orig_patent_app_number] => 10827675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/827675
Switchable clock source Apr 18, 2004 Issued
Array ( [id] => 550792 [patent_doc_number] => 07170332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Reference signal generators' [patent_app_type] => utility [patent_app_number] => 10/825891 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7186 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170332.pdf [firstpage_image] =>[orig_patent_app_number] => 10825891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/825891
Reference signal generators Apr 14, 2004 Issued
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