Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 509194 [patent_doc_number] => 07202714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator' [patent_app_type] => utility [patent_app_number] => 10/824361 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5778 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202714.pdf [firstpage_image] =>[orig_patent_app_number] => 10824361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/824361
Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator Apr 14, 2004 Issued
Array ( [id] => 752653 [patent_doc_number] => 07023263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Low pass filter' [patent_app_type] => utility [patent_app_number] => 10/709101 [patent_app_country] => US [patent_app_date] => 2004-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2559 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023263.pdf [firstpage_image] =>[orig_patent_app_number] => 10709101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709101
Low pass filter Apr 13, 2004 Issued
Array ( [id] => 7016937 [patent_doc_number] => 20050218955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Adaptive frequency clock generation system' [patent_app_type] => utility [patent_app_number] => 10/813551 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5001 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20050218955.pdf [firstpage_image] =>[orig_patent_app_number] => 10813551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813551
Adaptive frequency clock generation system Mar 30, 2004 Issued
Array ( [id] => 7016984 [patent_doc_number] => 20050219002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Tuning an oscillator' [patent_app_type] => utility [patent_app_number] => 10/814406 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3876 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219002.pdf [firstpage_image] =>[orig_patent_app_number] => 10814406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814406
Tuning an oscillator Mar 30, 2004 Abandoned
Array ( [id] => 7273515 [patent_doc_number] => 20040232966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Multiple clocks with superperiod' [patent_app_type] => new [patent_app_number] => 10/814021 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7687 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232966.pdf [firstpage_image] =>[orig_patent_app_number] => 10814021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814021
Multiple clocks with superperiod Mar 30, 2004 Issued
Array ( [id] => 946926 [patent_doc_number] => 06965260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'System and method for increasing effective pulse-width modulated drive signal resolution and converter controller incorporating the same' [patent_app_type] => utility [patent_app_number] => 10/812531 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3871 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965260.pdf [firstpage_image] =>[orig_patent_app_number] => 10812531 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/812531
System and method for increasing effective pulse-width modulated drive signal resolution and converter controller incorporating the same Mar 29, 2004 Issued
Array ( [id] => 651432 [patent_doc_number] => 07113010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Clock distortion detector using a synchronous mirror delay circuit' [patent_app_type] => utility [patent_app_number] => 10/809826 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4391 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113010.pdf [firstpage_image] =>[orig_patent_app_number] => 10809826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/809826
Clock distortion detector using a synchronous mirror delay circuit Mar 25, 2004 Issued
Array ( [id] => 5202844 [patent_doc_number] => 20070024323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Wide-band circuit' [patent_app_type] => utility [patent_app_number] => 10/551413 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 15992 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20070024323.pdf [firstpage_image] =>[orig_patent_app_number] => 10551413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/551413
Wide-band circuit coupled through a transmission line Mar 23, 2004 Issued
Array ( [id] => 793540 [patent_doc_number] => 06982586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Systems and methods for clock generation using hot-swappable oscillators' [patent_app_type] => utility [patent_app_number] => 10/805863 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982586.pdf [firstpage_image] =>[orig_patent_app_number] => 10805863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805863
Systems and methods for clock generation using hot-swappable oscillators Mar 21, 2004 Issued
Array ( [id] => 757017 [patent_doc_number] => 07019576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Delay circuit that scales with clock cycle time' [patent_app_type] => utility [patent_app_number] => 10/804988 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019576.pdf [firstpage_image] =>[orig_patent_app_number] => 10804988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/804988
Delay circuit that scales with clock cycle time Mar 17, 2004 Issued
Array ( [id] => 7273509 [patent_doc_number] => 20040232960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Phase-error-compensation techniques in a fractional-N PLL frequency synthesizer' [patent_app_type] => new [patent_app_number] => 10/801502 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6904 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232960.pdf [firstpage_image] =>[orig_patent_app_number] => 10801502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801502
Phase-error-compensation techniques in a fractional-N PLL frequency synthesizer Mar 14, 2004 Issued
Array ( [id] => 7424654 [patent_doc_number] => 20040183709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Analog signal level detecting apparatus' [patent_app_type] => new [patent_app_number] => 10/799668 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4090 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183709.pdf [firstpage_image] =>[orig_patent_app_number] => 10799668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799668
Analog signal level detecting apparatus Mar 14, 2004 Issued
Array ( [id] => 7059308 [patent_doc_number] => 20050001667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Delay circuit with more-responsively adapting delay time' [patent_app_type] => utility [patent_app_number] => 10/798560 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3633 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001667.pdf [firstpage_image] =>[orig_patent_app_number] => 10798560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798560
Delay circuit with more-responsively adapting delay time Mar 11, 2004 Issued
Array ( [id] => 7059330 [patent_doc_number] => 20050001689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Phase-locked loop circuit with switched-capacitor conditioning of the control current' [patent_app_type] => utility [patent_app_number] => 10/798244 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001689.pdf [firstpage_image] =>[orig_patent_app_number] => 10798244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798244
Phase-locked loop circuit with switched-capacitor conditioning of the control current Mar 10, 2004 Issued
Array ( [id] => 7616553 [patent_doc_number] => 06946890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Low noise level shifting circuits and methods and systems using the same' [patent_app_type] => utility [patent_app_number] => 10/798661 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946890.pdf [firstpage_image] =>[orig_patent_app_number] => 10798661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798661
Low noise level shifting circuits and methods and systems using the same Mar 10, 2004 Issued
Array ( [id] => 7607009 [patent_doc_number] => 07098707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Highly configurable PLL architecture for programmable logic' [patent_app_type] => utility [patent_app_number] => 10/797836 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6157 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098707.pdf [firstpage_image] =>[orig_patent_app_number] => 10797836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797836
Highly configurable PLL architecture for programmable logic Mar 8, 2004 Issued
Array ( [id] => 7177835 [patent_doc_number] => 20050189974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'A MULTI-STAGE DELAY CLOCK GENERATOR' [patent_app_type] => utility [patent_app_number] => 10/708373 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3403 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189974.pdf [firstpage_image] =>[orig_patent_app_number] => 10708373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708373
Multi-stage delay clock generator Feb 25, 2004 Issued
Array ( [id] => 7144673 [patent_doc_number] => 20040169538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'DLL circuit' [patent_app_type] => new [patent_app_number] => 10/785015 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8479 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20040169538.pdf [firstpage_image] =>[orig_patent_app_number] => 10785015 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785015
DLL circuit Feb 24, 2004 Issued
Array ( [id] => 7125549 [patent_doc_number] => 20050057293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Stable timing clock circuit' [patent_app_type] => utility [patent_app_number] => 10/781877 [patent_app_country] => US [patent_app_date] => 2004-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057293.pdf [firstpage_image] =>[orig_patent_app_number] => 10781877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781877
Stable timing clock circuit Feb 19, 2004 Issued
Array ( [id] => 938779 [patent_doc_number] => 06972608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Clock generating circuit with a frequency multiplying circuit' [patent_app_type] => utility [patent_app_number] => 10/778120 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5671 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972608.pdf [firstpage_image] =>[orig_patent_app_number] => 10778120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778120
Clock generating circuit with a frequency multiplying circuit Feb 16, 2004 Issued
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