Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7417505 [patent_doc_number] => 20040160281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Circuitry to reduce PLL lock acquisition time' [patent_app_type] => new [patent_app_number] => 10/780493 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3061 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160281.pdf [firstpage_image] =>[orig_patent_app_number] => 10780493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/780493
Circuitry to reduce PLL lock acquisition time Feb 16, 2004 Issued
Array ( [id] => 783728 [patent_doc_number] => 06992516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Pulse duty cycle automatic correction device and method thereof' [patent_app_type] => utility [patent_app_number] => 10/778402 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2943 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992516.pdf [firstpage_image] =>[orig_patent_app_number] => 10778402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778402
Pulse duty cycle automatic correction device and method thereof Feb 16, 2004 Issued
Array ( [id] => 976446 [patent_doc_number] => 06933790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/777481 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9132 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933790.pdf [firstpage_image] =>[orig_patent_app_number] => 10777481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777481
Phase locked loop circuit Feb 11, 2004 Issued
Array ( [id] => 7292407 [patent_doc_number] => 20040212410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Reduced-size integrated phase-locked loop' [patent_app_type] => new [patent_app_number] => 10/776931 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2635 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212410.pdf [firstpage_image] =>[orig_patent_app_number] => 10776931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776931
Reduced-size integrated phase-locked loop Feb 10, 2004 Issued
Array ( [id] => 485051 [patent_doc_number] => 07221203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Pulse-width modulator circuit and method for controlling a pulse width modulator circuit' [patent_app_type] => utility [patent_app_number] => 10/532821 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2340 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221203.pdf [firstpage_image] =>[orig_patent_app_number] => 10532821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/532821
Pulse-width modulator circuit and method for controlling a pulse width modulator circuit Jan 7, 2004 Issued
Array ( [id] => 7239271 [patent_doc_number] => 20050140415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Timing circuit for separate positive and negative edge placement in a switching DC-DC converter' [patent_app_type] => utility [patent_app_number] => 10/748298 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4384 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140415.pdf [firstpage_image] =>[orig_patent_app_number] => 10748298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748298
Timing circuit for separate positive and negative edge placement in a switching DC-DC converter Dec 30, 2003 Issued
Array ( [id] => 7239262 [patent_doc_number] => 20050140412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver' [patent_app_type] => utility [patent_app_number] => 10/748300 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4745 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140412.pdf [firstpage_image] =>[orig_patent_app_number] => 10748300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748300
Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver Dec 30, 2003 Issued
Array ( [id] => 7200371 [patent_doc_number] => 20050052214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Level shifter circuit' [patent_app_type] => utility [patent_app_number] => 10/747240 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8546 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052214.pdf [firstpage_image] =>[orig_patent_app_number] => 10747240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747240
Level shifter circuit Dec 29, 2003 Abandoned
Array ( [id] => 7239273 [patent_doc_number] => 20050140416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Programmable direct interpolating delay locked loop' [patent_app_type] => utility [patent_app_number] => 10/746105 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3760 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140416.pdf [firstpage_image] =>[orig_patent_app_number] => 10746105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746105
Programmable direct interpolating delay locked loop Dec 23, 2003 Issued
Array ( [id] => 712707 [patent_doc_number] => 07057428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Circuit for generating phase comparison signal' [patent_app_type] => utility [patent_app_number] => 10/746519 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2385 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057428.pdf [firstpage_image] =>[orig_patent_app_number] => 10746519 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746519
Circuit for generating phase comparison signal Dec 23, 2003 Issued
Array ( [id] => 883949 [patent_doc_number] => RE040168 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-03-25 [patent_title] => 'Low power circuit with proper slew rate by automatic adjustment of bias current' [patent_app_type] => reissue [patent_app_number] => 10/740901 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040168.pdf [firstpage_image] =>[orig_patent_app_number] => 10740901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/740901
Low power circuit with proper slew rate by automatic adjustment of bias current Dec 21, 2003 Issued
Array ( [id] => 7607002 [patent_doc_number] => 07098714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Centralizing the lock point of a synchronous circuit' [patent_app_type] => utility [patent_app_number] => 10/730609 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9850 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098714.pdf [firstpage_image] =>[orig_patent_app_number] => 10730609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730609
Centralizing the lock point of a synchronous circuit Dec 7, 2003 Issued
Array ( [id] => 7614833 [patent_doc_number] => 06897695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Semiconductor integrated circuit device and method of detecting delay error in the same' [patent_app_type] => utility [patent_app_number] => 10/729457 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7195 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897695.pdf [firstpage_image] =>[orig_patent_app_number] => 10729457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729457
Semiconductor integrated circuit device and method of detecting delay error in the same Dec 4, 2003 Issued
Array ( [id] => 938778 [patent_doc_number] => 06972607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Clock signal regeneration circuitry' [patent_app_type] => utility [patent_app_number] => 10/728262 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2959 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972607.pdf [firstpage_image] =>[orig_patent_app_number] => 10728262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728262
Clock signal regeneration circuitry Dec 3, 2003 Issued
Array ( [id] => 669252 [patent_doc_number] => 07095264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Programmable jitter signal generator' [patent_app_type] => utility [patent_app_number] => 10/725847 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2472 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095264.pdf [firstpage_image] =>[orig_patent_app_number] => 10725847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725847
Programmable jitter signal generator Dec 1, 2003 Issued
Array ( [id] => 7319417 [patent_doc_number] => 20040135606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Circuit and method for inducing jitter to a signal' [patent_app_type] => new [patent_app_number] => 10/726079 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5848 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135606.pdf [firstpage_image] =>[orig_patent_app_number] => 10726079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726079
Circuit and method for inducing jitter to a signal Nov 30, 2003 Issued
Array ( [id] => 7461675 [patent_doc_number] => 20040095163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Single-ended differential circuit using complementary devices' [patent_app_type] => new [patent_app_number] => 10/714844 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6994 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095163.pdf [firstpage_image] =>[orig_patent_app_number] => 10714844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714844
Single-ended differential circuit using complementary devices Nov 17, 2003 Issued
Array ( [id] => 7454942 [patent_doc_number] => 20040100331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Apparatus for controlling the frequency of received signals to a predetermined frequency' [patent_app_type] => new [patent_app_number] => 10/712055 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4683 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20040100331.pdf [firstpage_image] =>[orig_patent_app_number] => 10712055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712055
Apparatus for controlling the frequency of received signals to a predetermined frequency Nov 13, 2003 Issued
Array ( [id] => 7101941 [patent_doc_number] => 20050104667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Frequency synthesizer having PLL with an analog phase detector' [patent_app_type] => utility [patent_app_number] => 10/713717 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104667.pdf [firstpage_image] =>[orig_patent_app_number] => 10713717 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713717
Frequency synthesizer having PLL with an analog phase detector Nov 13, 2003 Issued
Array ( [id] => 432813 [patent_doc_number] => 07265590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit' [patent_app_type] => utility [patent_app_number] => 10/713365 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7322 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265590.pdf [firstpage_image] =>[orig_patent_app_number] => 10713365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713365
Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit Nov 13, 2003 Issued
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