Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6916033 [patent_doc_number] => 20050093594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'DELAY LOCKED LOOP PHASE BLENDER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 10/696920 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4549 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093594.pdf [firstpage_image] =>[orig_patent_app_number] => 10696920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696920
DELAY LOCKED LOOP PHASE BLENDER CIRCUIT Oct 29, 2003 Abandoned
Array ( [id] => 979517 [patent_doc_number] => 06930523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Apparatus and method for reflection delay splitting digital clock distribution' [patent_app_type] => utility [patent_app_number] => 10/697131 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3261 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930523.pdf [firstpage_image] =>[orig_patent_app_number] => 10697131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697131
Apparatus and method for reflection delay splitting digital clock distribution Oct 29, 2003 Issued
Array ( [id] => 6916030 [patent_doc_number] => 20050093591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semidigital delay-locked loop using an analog-based finite state machine' [patent_app_type] => utility [patent_app_number] => 10/696139 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4493 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093591.pdf [firstpage_image] =>[orig_patent_app_number] => 10696139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696139
Semidigital delay-locked loop using an analog-based finite state machine Oct 28, 2003 Issued
Array ( [id] => 7155567 [patent_doc_number] => 20050083089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/691152 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4190 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083089.pdf [firstpage_image] =>[orig_patent_app_number] => 10691152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691152
Programmable phase-locked loop circuitry for programmable logic device Oct 20, 2003 Issued
Array ( [id] => 1083827 [patent_doc_number] => 06833744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Circuit for correcting duty factor of clock signal' [patent_app_type] => B2 [patent_app_number] => 10/688685 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833744.pdf [firstpage_image] =>[orig_patent_app_number] => 10688685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688685
Circuit for correcting duty factor of clock signal Oct 16, 2003 Issued
Array ( [id] => 7296625 [patent_doc_number] => 20040124931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Circular geometry oscillators' [patent_app_type] => new [patent_app_number] => 10/687679 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3070 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124931.pdf [firstpage_image] =>[orig_patent_app_number] => 10687679 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687679
Circular geometry oscillators Oct 16, 2003 Issued
Array ( [id] => 1054135 [patent_doc_number] => 06859073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Fast VCO calibration for frequency synthesizers' [patent_app_type] => utility [patent_app_number] => 10/687492 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 1703 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859073.pdf [firstpage_image] =>[orig_patent_app_number] => 10687492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687492
Fast VCO calibration for frequency synthesizers Oct 16, 2003 Issued
Array ( [id] => 500721 [patent_doc_number] => 07208988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Clock generator' [patent_app_type] => utility [patent_app_number] => 10/684704 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6823 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208988.pdf [firstpage_image] =>[orig_patent_app_number] => 10684704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684704
Clock generator Oct 14, 2003 Issued
Array ( [id] => 726394 [patent_doc_number] => 07046065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Decimal set point clock generator and application of this clock generator to UART circuit' [patent_app_type] => utility [patent_app_number] => 10/684823 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7150 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046065.pdf [firstpage_image] =>[orig_patent_app_number] => 10684823 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684823
Decimal set point clock generator and application of this clock generator to UART circuit Oct 13, 2003 Issued
Array ( [id] => 793530 [patent_doc_number] => 06982576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Signal delay compensating circuit' [patent_app_type] => utility [patent_app_number] => 10/684187 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3842 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982576.pdf [firstpage_image] =>[orig_patent_app_number] => 10684187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684187
Signal delay compensating circuit Oct 9, 2003 Issued
Array ( [id] => 7273516 [patent_doc_number] => 20040232967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit' [patent_app_type] => new [patent_app_number] => 10/682166 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12623 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232967.pdf [firstpage_image] =>[orig_patent_app_number] => 10682166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682166
Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit Oct 9, 2003 Issued
Array ( [id] => 1019037 [patent_doc_number] => 06891408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Current pulse receiving circuit' [patent_app_type] => utility [patent_app_number] => 10/681306 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15454 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891408.pdf [firstpage_image] =>[orig_patent_app_number] => 10681306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681306
Current pulse receiving circuit Oct 8, 2003 Issued
Array ( [id] => 7612255 [patent_doc_number] => 06903582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Integrated circuit timing debug apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/682351 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903582.pdf [firstpage_image] =>[orig_patent_app_number] => 10682351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682351
Integrated circuit timing debug apparatus and method Oct 8, 2003 Issued
Array ( [id] => 7436334 [patent_doc_number] => 20040066216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Differential output structure with reduced skew for a single input' [patent_app_type] => new [patent_app_number] => 10/678937 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066216.pdf [firstpage_image] =>[orig_patent_app_number] => 10678937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/678937
Differential output structure with reduced skew for a single input Oct 2, 2003 Issued
Array ( [id] => 1057234 [patent_doc_number] => 06856174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Versatile system for high resolution device calibration' [patent_app_type] => utility [patent_app_number] => 10/677105 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4357 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856174.pdf [firstpage_image] =>[orig_patent_app_number] => 10677105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677105
Versatile system for high resolution device calibration Sep 30, 2003 Issued
Array ( [id] => 969045 [patent_doc_number] => 06940323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Phase locked loop circuit with an unlock detection circuit and a switch' [patent_app_type] => utility [patent_app_number] => 10/670516 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8318 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940323.pdf [firstpage_image] =>[orig_patent_app_number] => 10670516 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670516
Phase locked loop circuit with an unlock detection circuit and a switch Sep 25, 2003 Issued
Array ( [id] => 7292410 [patent_doc_number] => 20040212413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'DLL Circuit' [patent_app_type] => new [patent_app_number] => 10/672990 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5060 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212413.pdf [firstpage_image] =>[orig_patent_app_number] => 10672990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/672990
DLL circuit Sep 25, 2003 Issued
Array ( [id] => 7619591 [patent_doc_number] => 06943595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Synchronization circuit' [patent_app_type] => utility [patent_app_number] => 10/670510 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8693 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943595.pdf [firstpage_image] =>[orig_patent_app_number] => 10670510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670510
Synchronization circuit Sep 25, 2003 Issued
Array ( [id] => 997038 [patent_doc_number] => 06914463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Frequency output generation through alternating between selected frequencies' [patent_app_type] => utility [patent_app_number] => 10/671431 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5930 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914463.pdf [firstpage_image] =>[orig_patent_app_number] => 10671431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/671431
Frequency output generation through alternating between selected frequencies Sep 25, 2003 Issued
Array ( [id] => 1086862 [patent_doc_number] => 06831506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Reconfigurable filter architecture' [patent_app_type] => B1 [patent_app_number] => 10/665234 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2555 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831506.pdf [firstpage_image] =>[orig_patent_app_number] => 10665234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665234
Reconfigurable filter architecture Sep 16, 2003 Issued
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