
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6916033
[patent_doc_number] => 20050093594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'DELAY LOCKED LOOP PHASE BLENDER CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 10/696920
[patent_app_country] => US
[patent_app_date] => 2003-10-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/696920 | DELAY LOCKED LOOP PHASE BLENDER CIRCUIT | Oct 29, 2003 | Abandoned |
Array
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[patent_doc_number] => 06930523
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[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Apparatus and method for reflection delay splitting digital clock distribution'
[patent_app_type] => utility
[patent_app_number] => 10/697131
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697131 | Apparatus and method for reflection delay splitting digital clock distribution | Oct 29, 2003 | Issued |
Array
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[patent_issue_date] => 2005-05-05
[patent_title] => 'Semidigital delay-locked loop using an analog-based finite state machine'
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Array
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[patent_doc_number] => 20050083089
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[patent_issue_date] => 2005-04-21
[patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device'
[patent_app_type] => utility
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Array
(
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[patent_issue_date] => 2004-12-21
[patent_title] => 'Circuit for correcting duty factor of clock signal'
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Array
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Array
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[patent_title] => 'Fast VCO calibration for frequency synthesizers'
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Array
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[patent_doc_number] => 07208988
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[patent_issue_date] => 2007-04-24
[patent_title] => 'Clock generator'
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Array
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[id] => 726394
[patent_doc_number] => 07046065
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[patent_kind] => B2
[patent_issue_date] => 2006-05-16
[patent_title] => 'Decimal set point clock generator and application of this clock generator to UART circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684823 | Decimal set point clock generator and application of this clock generator to UART circuit | Oct 13, 2003 | Issued |
Array
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[patent_doc_number] => 06982576
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[patent_issue_date] => 2006-01-03
[patent_title] => 'Signal delay compensating circuit'
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[patent_app_number] => 10/684187
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Array
(
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[patent_doc_number] => 20040232967
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[patent_title] => 'Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit'
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Array
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Array
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Array
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Array
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