Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1044488 [patent_doc_number] => 06867627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics' [patent_app_type] => utility [patent_app_number] => 10/663624 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867627.pdf [firstpage_image] =>[orig_patent_app_number] => 10663624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663624
Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics Sep 15, 2003 Issued
Array ( [id] => 7355555 [patent_doc_number] => 20040090255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Delay circuit with delay relatively independent of process, voltage, and temperature variations' [patent_app_type] => new [patent_app_number] => 10/661563 [patent_app_country] => US [patent_app_date] => 2003-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4607 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090255.pdf [firstpage_image] =>[orig_patent_app_number] => 10661563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/661563
Delay circuit and method with delay relatively independent of process, voltage, and temperature variations Sep 14, 2003 Issued
Array ( [id] => 1064088 [patent_doc_number] => 06850101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Single-line synchronizable oscillator circuit' [patent_app_type] => utility [patent_app_number] => 10/657506 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850101.pdf [firstpage_image] =>[orig_patent_app_number] => 10657506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657506
Single-line synchronizable oscillator circuit Sep 7, 2003 Issued
Array ( [id] => 7059307 [patent_doc_number] => 20050001666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'DELAY CIRCUIT HAVING FUNCTION OF FILTER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 10/656254 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5241 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001666.pdf [firstpage_image] =>[orig_patent_app_number] => 10656254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/656254
Delay circuit having function of filter circuit Sep 7, 2003 Issued
Array ( [id] => 775109 [patent_doc_number] => 07002383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)' [patent_app_type] => utility [patent_app_number] => 10/654711 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2403 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002383.pdf [firstpage_image] =>[orig_patent_app_number] => 10654711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654711
Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL) Sep 3, 2003 Issued
Array ( [id] => 1094280 [patent_doc_number] => 06825703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Delay locked loop and method of driving the same' [patent_app_type] => B1 [patent_app_number] => 10/654498 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2711 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825703.pdf [firstpage_image] =>[orig_patent_app_number] => 10654498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654498
Delay locked loop and method of driving the same Sep 2, 2003 Issued
Array ( [id] => 7081072 [patent_doc_number] => 20050046452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'All digital PLL trimming circuit' [patent_app_type] => utility [patent_app_number] => 10/653614 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5975 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20050046452.pdf [firstpage_image] =>[orig_patent_app_number] => 10653614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653614
All digital PLL trimming circuit Sep 1, 2003 Issued
Array ( [id] => 620684 [patent_doc_number] => 07142042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Nulled error amplifier' [patent_app_type] => utility [patent_app_number] => 10/651849 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3895 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142042.pdf [firstpage_image] =>[orig_patent_app_number] => 10651849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651849
Nulled error amplifier Aug 28, 2003 Issued
Array ( [id] => 7382140 [patent_doc_number] => 20040036515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method and circuit for adjusting the timing of output data based on an operational mode of output drivers' [patent_app_type] => new [patent_app_number] => 10/651602 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8226 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036515.pdf [firstpage_image] =>[orig_patent_app_number] => 10651602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651602
Method and circuit for adjusting the timing of output data based on an operational mode of output drivers Aug 28, 2003 Issued
Array ( [id] => 1041379 [patent_doc_number] => 06870404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Programmable differential capacitors for equalization circuits' [patent_app_type] => utility [patent_app_number] => 10/652863 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4112 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870404.pdf [firstpage_image] =>[orig_patent_app_number] => 10652863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/652863
Programmable differential capacitors for equalization circuits Aug 27, 2003 Issued
Array ( [id] => 1083820 [patent_doc_number] => 06833740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Sinusoidal frequency generator and periodic signal converter using thereof' [patent_app_type] => B2 [patent_app_number] => 10/649711 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833740.pdf [firstpage_image] =>[orig_patent_app_number] => 10649711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649711
Sinusoidal frequency generator and periodic signal converter using thereof Aug 25, 2003 Issued
Array ( [id] => 7377234 [patent_doc_number] => 20040178834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Phase-locked loop integrated circuits that support clock signal updates during dead zone compensation time intervals' [patent_app_type] => new [patent_app_number] => 10/640075 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4305 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178834.pdf [firstpage_image] =>[orig_patent_app_number] => 10640075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640075
Phase-locked loop integrated circuits that support clock signal updates during dead zone compensation time intervals Aug 12, 2003 Issued
Array ( [id] => 1022853 [patent_doc_number] => 06888385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Phase locked loop (PLL) for integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/639248 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2018 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888385.pdf [firstpage_image] =>[orig_patent_app_number] => 10639248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/639248
Phase locked loop (PLL) for integrated circuits Aug 11, 2003 Issued
Array ( [id] => 7355533 [patent_doc_number] => 20040090248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Programmable timing generator with offset and width control using delay lock loop' [patent_app_type] => new [patent_app_number] => 10/637401 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1887 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090248.pdf [firstpage_image] =>[orig_patent_app_number] => 10637401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637401
Programmable timing generator with offset and width control using delay lock loop Aug 7, 2003 Abandoned
Array ( [id] => 991218 [patent_doc_number] => 06919745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Ring-resister controlled DLL with fine delay line and direct skew sensing detector' [patent_app_type] => utility [patent_app_number] => 10/635913 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7741 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919745.pdf [firstpage_image] =>[orig_patent_app_number] => 10635913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635913
Ring-resister controlled DLL with fine delay line and direct skew sensing detector Aug 6, 2003 Issued
Array ( [id] => 1098007 [patent_doc_number] => 06822486 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Multiplexer methods and apparatus' [patent_app_type] => B1 [patent_app_number] => 10/635968 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4233 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822486.pdf [firstpage_image] =>[orig_patent_app_number] => 10635968 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635968
Multiplexer methods and apparatus Aug 6, 2003 Issued
Array ( [id] => 7627692 [patent_doc_number] => 06806746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Direct frequency synthesizer for offset loop synthesizer' [patent_app_type] => B1 [patent_app_number] => 10/633225 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806746.pdf [firstpage_image] =>[orig_patent_app_number] => 10633225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633225
Direct frequency synthesizer for offset loop synthesizer Jul 30, 2003 Issued
Array ( [id] => 7149048 [patent_doc_number] => 20050024116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Delay matching for clock distribution in a logic circuit' [patent_app_type] => utility [patent_app_number] => 10/632651 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4339 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024116.pdf [firstpage_image] =>[orig_patent_app_number] => 10632651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632651
Delay matching for clock distribution in a logic circuit Jul 30, 2003 Issued
Array ( [id] => 1109615 [patent_doc_number] => 06809566 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Low power differential-to-single-ended converter with good duty cycle performance' [patent_app_type] => B1 [patent_app_number] => 10/630153 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809566.pdf [firstpage_image] =>[orig_patent_app_number] => 10630153 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630153
Low power differential-to-single-ended converter with good duty cycle performance Jul 29, 2003 Issued
Array ( [id] => 7629205 [patent_doc_number] => 06819152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices' [patent_app_type] => B1 [patent_app_number] => 10/630311 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819152.pdf [firstpage_image] =>[orig_patent_app_number] => 10630311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630311
Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices Jul 29, 2003 Issued
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