Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 712703 [patent_doc_number] => 07057426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Frequency converter, orthogonal demodulator and orthogonal modulator' [patent_app_type] => utility [patent_app_number] => 10/622434 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5781 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057426.pdf [firstpage_image] =>[orig_patent_app_number] => 10622434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622434
Frequency converter, orthogonal demodulator and orthogonal modulator Jul 20, 2003 Issued
Array ( [id] => 7120695 [patent_doc_number] => 20050012524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'PLL lock detection circuit using edge detection' [patent_app_type] => utility [patent_app_number] => 10/622627 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4713 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012524.pdf [firstpage_image] =>[orig_patent_app_number] => 10622627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622627
PLL lock detection circuit using edge detection Jul 16, 2003 Issued
Array ( [id] => 997040 [patent_doc_number] => 06914464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Phase locked loop circuit using fractional frequency divider' [patent_app_type] => utility [patent_app_number] => 10/620509 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3794 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914464.pdf [firstpage_image] =>[orig_patent_app_number] => 10620509 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620509
Phase locked loop circuit using fractional frequency divider Jul 15, 2003 Issued
Array ( [id] => 1125811 [patent_doc_number] => 06794917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'System and method for generating minimum on-time pulses' [patent_app_type] => B1 [patent_app_number] => 10/620100 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794917.pdf [firstpage_image] =>[orig_patent_app_number] => 10620100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620100
System and method for generating minimum on-time pulses Jul 13, 2003 Issued
Array ( [id] => 7121242 [patent_doc_number] => 20050013071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Slew rate at buffers by isolating predriver from driver' [patent_app_type] => utility [patent_app_number] => 10/618479 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3059 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013071.pdf [firstpage_image] =>[orig_patent_app_number] => 10618479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618479
Slew rate at buffers by isolating predriver from driver Jul 10, 2003 Issued
Array ( [id] => 6988700 [patent_doc_number] => 20050087813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Direct conversion receiver using vertical bipolar junction transistor available in deep n-well cmos technology' [patent_app_type] => utility [patent_app_number] => 10/504366 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6132 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20050087813.pdf [firstpage_image] =>[orig_patent_app_number] => 10504366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/504366
Direct conversion receiver using vertical bipolar junction transistor available in deep n-well CMOS technology Jul 10, 2003 Issued
Array ( [id] => 7382105 [patent_doc_number] => 20040036509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Frequency synthesizer' [patent_app_type] => new [patent_app_number] => 10/615992 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1858 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036509.pdf [firstpage_image] =>[orig_patent_app_number] => 10615992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615992
Frequency synthesizer Jul 9, 2003 Issued
Array ( [id] => 7398442 [patent_doc_number] => 20040104751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Conditional clock buffer circuit' [patent_app_type] => new [patent_app_number] => 10/617080 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20040104751.pdf [firstpage_image] =>[orig_patent_app_number] => 10617080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617080
Conditional clock buffer circuit Jul 9, 2003 Issued
Array ( [id] => 7087053 [patent_doc_number] => 20050007165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method and apparatus for determining a processing speed of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/614769 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4181 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007165.pdf [firstpage_image] =>[orig_patent_app_number] => 10614769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614769
Method and apparatus for determining a processing speed of an integrated circuit Jul 7, 2003 Issued
Array ( [id] => 1133560 [patent_doc_number] => 06788135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Terminating pathway for a clock signal' [patent_app_type] => B1 [patent_app_number] => 10/615549 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3258 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788135.pdf [firstpage_image] =>[orig_patent_app_number] => 10615549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615549
Terminating pathway for a clock signal Jul 7, 2003 Issued
Array ( [id] => 7408242 [patent_doc_number] => 20040263212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Circuit for controlling the performance of an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/611131 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20040263212.pdf [firstpage_image] =>[orig_patent_app_number] => 10611131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611131
Circuit for controlling the performance of an integrated circuit Jun 29, 2003 Issued
Array ( [id] => 1098022 [patent_doc_number] => 06822490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Data output circuit for reducing skew of data signal' [patent_app_type] => B2 [patent_app_number] => 10/609896 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 13241 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822490.pdf [firstpage_image] =>[orig_patent_app_number] => 10609896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609896
Data output circuit for reducing skew of data signal Jun 29, 2003 Issued
Array ( [id] => 1028748 [patent_doc_number] => 06882195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Signal timing adjustment circuit with external resistor' [patent_app_type] => utility [patent_app_number] => 10/608747 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3943 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882195.pdf [firstpage_image] =>[orig_patent_app_number] => 10608747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608747
Signal timing adjustment circuit with external resistor Jun 26, 2003 Issued
Array ( [id] => 1098027 [patent_doc_number] => 06822491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Frequency prescaler apparatus, method, and system' [patent_app_type] => B1 [patent_app_number] => 10/608051 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4689 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822491.pdf [firstpage_image] =>[orig_patent_app_number] => 10608051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608051
Frequency prescaler apparatus, method, and system Jun 26, 2003 Issued
Array ( [id] => 1097999 [patent_doc_number] => 06822484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'High-frequency phase/frequency detector with improved reset mechanism' [patent_app_type] => B1 [patent_app_number] => 10/606583 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2928 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822484.pdf [firstpage_image] =>[orig_patent_app_number] => 10606583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606583
High-frequency phase/frequency detector with improved reset mechanism Jun 25, 2003 Issued
Array ( [id] => 7408329 [patent_doc_number] => 20040263223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'CASCADED PHASE-LOCKED LOOPS' [patent_app_type] => new [patent_app_number] => 10/603722 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1902 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20040263223.pdf [firstpage_image] =>[orig_patent_app_number] => 10603722 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603722
Cascaded phase-locked loops Jun 23, 2003 Issued
Array ( [id] => 7238378 [patent_doc_number] => 20040257118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'System and method for dead-band determination for rotational frequency detectors' [patent_app_type] => new [patent_app_number] => 10/601993 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5692 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257118.pdf [firstpage_image] =>[orig_patent_app_number] => 10601993 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/601993
System and method for dead-band determination for rotational frequency detectors Jun 22, 2003 Issued
Array ( [id] => 976374 [patent_doc_number] => 06933761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Techniques for dynamically selecting phases of oscillator signals' [patent_app_type] => utility [patent_app_number] => 10/600120 [patent_app_country] => US [patent_app_date] => 2003-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4629 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933761.pdf [firstpage_image] =>[orig_patent_app_number] => 10600120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/600120
Techniques for dynamically selecting phases of oscillator signals Jun 19, 2003 Issued
Array ( [id] => 7626397 [patent_doc_number] => 06768366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Charge pump system and clock generator' [patent_app_type] => B2 [patent_app_number] => 10/462861 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 2231 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768366.pdf [firstpage_image] =>[orig_patent_app_number] => 10462861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462861
Charge pump system and clock generator Jun 16, 2003 Issued
Array ( [id] => 7612251 [patent_doc_number] => 06903586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Gain control circuitry for delay locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/463391 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6956 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903586.pdf [firstpage_image] =>[orig_patent_app_number] => 10463391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463391
Gain control circuitry for delay locked loop circuit Jun 16, 2003 Issued
Menu