Linh M. Nguyen

Array ( [id] => 1106837 [patent_doc_number] => 06812750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Divided clock generation' [patent_app_type] => B1 [patent_app_number] => 10/461088 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8541 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812750.pdf [firstpage_image] =>[orig_patent_app_number] => 10461088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1098053 [patent_doc_number] => 06822497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Clock generator' [patent_app_type] => B1 [patent_app_number] => 10/460959 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2993 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822497.pdf [firstpage_image] =>[orig_patent_app_number] => 10460959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 969044 [patent_doc_number] => 06940322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'High speed phase locked loop' [patent_app_type] => utility [patent_app_number] => 10/459910 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2263 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940322.pdf [firstpage_image] =>[orig_patent_app_number] => 10459910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1116788 [patent_doc_number] => 06804812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Depopulated programmable logic array' [patent_app_type] => B2 [patent_app_number] => 10/458892 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 5687 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804812.pdf [firstpage_image] =>[orig_patent_app_number] => 10458892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824050 [patent_doc_number] => 20030234672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Clock signal generation circuit and audio data processing apparatus' [patent_app_type] => new [patent_app_number] => 10/457560 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4324 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20030234672.pdf [firstpage_image] =>[orig_patent_app_number] => 10457560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7273505 [patent_doc_number] => 20040232956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Synchronized clocking' [patent_app_type] => new [patent_app_number] => 10/443436 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4462 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232956.pdf [firstpage_image] =>[orig_patent_app_number] => 10443436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7292405 [patent_doc_number] => 20040212408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Pulse generating circuit and high-side driver circuit' [patent_app_type] => new [patent_app_number] => 10/443094 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5957 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212408.pdf [firstpage_image] =>[orig_patent_app_number] => 10443094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1121623 [patent_doc_number] => 06798261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method and apparatus for characterizing switching history impact' [patent_app_type] => B1 [patent_app_number] => 10/443515 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6754 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798261.pdf [firstpage_image] =>[orig_patent_app_number] => 10443515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1086825 [patent_doc_number] => 06831489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Low-voltage high-speed frequency-divider circuit' [patent_app_type] => B2 [patent_app_number] => 10/442168 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2461 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831489.pdf [firstpage_image] =>[orig_patent_app_number] => 10442168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7422750 [patent_doc_number] => 20040000937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'DLL with false lock protector' [patent_app_type] => new [patent_app_number] => 10/437417 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3198 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20040000937.pdf [firstpage_image] =>[orig_patent_app_number] => 10437417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6768397 [patent_doc_number] => 20030214337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Latch circuit' [patent_app_type] => new [patent_app_number] => 10/434332 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4860 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214337.pdf [firstpage_image] =>[orig_patent_app_number] => 10434332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1181288 [patent_doc_number] => 06744296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Circuits and methods for accurately setting a phase shift' [patent_app_type] => B1 [patent_app_number] => 10/430837 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5521 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744296.pdf [firstpage_image] =>[orig_patent_app_number] => 10430837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6768395 [patent_doc_number] => 20030214335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Clock and data recovery circuit and clock control method thereof' [patent_app_type] => new [patent_app_number] => 10/427928 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8580 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214335.pdf [firstpage_image] =>[orig_patent_app_number] => 10427928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1109547 [patent_doc_number] => 06809555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Glitch-free digital phase detector circuits and methods with optional offset and lock window extension' [patent_app_type] => B1 [patent_app_number] => 10/428342 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6144 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809555.pdf [firstpage_image] =>[orig_patent_app_number] => 10428342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7364619 [patent_doc_number] => 20040217794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Propagation delay adjustment circuit' [patent_app_type] => new [patent_app_number] => 10/427557 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7820 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217794.pdf [firstpage_image] =>[orig_patent_app_number] => 10427557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 513823 [patent_doc_number] => 07199624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Phase locked loop system capable of deskewing' [patent_app_type] => utility [patent_app_number] => 10/425914 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5727 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199624.pdf [firstpage_image] =>[orig_patent_app_number] => 10425914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1083830 [patent_doc_number] => 06833745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Signal generator for charge pump in an integrated circuit' [patent_app_type] => B2 [patent_app_number] => 10/426011 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3218 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833745.pdf [firstpage_image] =>[orig_patent_app_number] => 10426011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7293963 [patent_doc_number] => 20040213357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method and apparatus for conversionless direct detection' [patent_app_type] => new [patent_app_number] => 10/424377 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7021 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213357.pdf [firstpage_image] =>[orig_patent_app_number] => 10424377 [rel_patent_id] =>[rel_patent_doc_number] =>)