Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1009910 [patent_doc_number] => 06900674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method and circuitry for phase align detection in multi-clock domain' [patent_app_type] => utility [patent_app_number] => 10/375587 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3154 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900674.pdf [firstpage_image] =>[orig_patent_app_number] => 10375587 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375587
Method and circuitry for phase align detection in multi-clock domain Feb 26, 2003 Issued
Array ( [id] => 961410 [patent_doc_number] => 06952123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'System with dual rail regulated locked loop' [patent_app_type] => utility [patent_app_number] => 10/374252 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 51 [patent_no_of_words] => 31394 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952123.pdf [firstpage_image] =>[orig_patent_app_number] => 10374252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/374252
System with dual rail regulated locked loop Feb 24, 2003 Issued
Array ( [id] => 1169429 [patent_doc_number] => 06759881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'System with phase jumping locked loop circuit' [patent_app_type] => B2 [patent_app_number] => 10/374390 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 26773 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759881.pdf [firstpage_image] =>[orig_patent_app_number] => 10374390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/374390
System with phase jumping locked loop circuit Feb 24, 2003 Issued
Array ( [id] => 1022857 [patent_doc_number] => 06888387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => utility [patent_app_number] => 10/371248 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14328 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888387.pdf [firstpage_image] =>[orig_patent_app_number] => 10371248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/371248
Clock controlling method and circuit Feb 19, 2003 Issued
Array ( [id] => 6854558 [patent_doc_number] => 20030128059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => new [patent_app_number] => 10/370641 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14417 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128059.pdf [firstpage_image] =>[orig_patent_app_number] => 10370641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/370641
Clock controlling method and circuit with a multi-phase multiplication clock generating circuit Feb 19, 2003 Issued
Array ( [id] => 1177065 [patent_doc_number] => 06750687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method and apparatus for phase aligning two clock signals utilizing a programmable phase adjustment circuit' [patent_app_type] => B1 [patent_app_number] => 10/366301 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8139 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750687.pdf [firstpage_image] =>[orig_patent_app_number] => 10366301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366301
Method and apparatus for phase aligning two clock signals utilizing a programmable phase adjustment circuit Feb 12, 2003 Issued
Array ( [id] => 7417304 [patent_doc_number] => 20040160253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Self alignment system for complement clocks' [patent_app_type] => new [patent_app_number] => 10/364716 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6528 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160253.pdf [firstpage_image] =>[orig_patent_app_number] => 10364716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364716
Self alignment system for complement clocks Feb 10, 2003 Issued
Array ( [id] => 1050994 [patent_doc_number] => 06861883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Semiconductor integrated circuit for phase management of clock domains including PLL circuit' [patent_app_type] => utility [patent_app_number] => 10/360754 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7794 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861883.pdf [firstpage_image] =>[orig_patent_app_number] => 10360754 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360754
Semiconductor integrated circuit for phase management of clock domains including PLL circuit Feb 9, 2003 Issued
Array ( [id] => 624126 [patent_doc_number] => 07138837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Digital phase locked loop circuitry and methods' [patent_app_type] => utility [patent_app_number] => 10/349541 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5083 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138837.pdf [firstpage_image] =>[orig_patent_app_number] => 10349541 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349541
Digital phase locked loop circuitry and methods Jan 20, 2003 Issued
Array ( [id] => 1047718 [patent_doc_number] => 06864727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Pulse generator with polarity control' [patent_app_type] => utility [patent_app_number] => 10/340494 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3513 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864727.pdf [firstpage_image] =>[orig_patent_app_number] => 10340494 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340494
Pulse generator with polarity control Jan 9, 2003 Issued
95/000007 DIGITAL VIDEO DISC VEHICLE TELEVISION Dec 15, 2002 Issued
Array ( [id] => 6854563 [patent_doc_number] => 20030128064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Variable delay circuit and a testing apparatus for a semiconductor circuit' [patent_app_type] => new [patent_app_number] => 10/306129 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6974 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128064.pdf [firstpage_image] =>[orig_patent_app_number] => 10306129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/306129
Variable delay circuit and a testing apparatus for a semiconductor circuit Nov 26, 2002 Issued
Array ( [id] => 6764328 [patent_doc_number] => 20030098726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Jittery polyphase clock' [patent_app_type] => new [patent_app_number] => 10/304667 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3194 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20030098726.pdf [firstpage_image] =>[orig_patent_app_number] => 10304667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304667
Jittery polyphase clock Nov 24, 2002 Issued
Array ( [id] => 7629189 [patent_doc_number] => 06819168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Integrator with high gain and fast transient response' [patent_app_type] => B1 [patent_app_number] => 10/294853 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4713 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819168.pdf [firstpage_image] =>[orig_patent_app_number] => 10294853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/294853
Integrator with high gain and fast transient response Nov 13, 2002 Issued
Array ( [id] => 651437 [patent_doc_number] => 07113015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Circuit for setting a signal propagation time for a signal on a signal line and method for ascertaining timing parameters' [patent_app_type] => utility [patent_app_number] => 10/291069 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4143 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113015.pdf [firstpage_image] =>[orig_patent_app_number] => 10291069 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291069
Circuit for setting a signal propagation time for a signal on a signal line and method for ascertaining timing parameters Nov 7, 2002 Issued
Array ( [id] => 6854561 [patent_doc_number] => 20030128062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Delay circuit and synchronous delay apparatus' [patent_app_type] => new [patent_app_number] => 10/279498 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128062.pdf [firstpage_image] =>[orig_patent_app_number] => 10279498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279498
Delay circuit and synchronous delay apparatus Oct 24, 2002 Issued
Array ( [id] => 1117274 [patent_doc_number] => 06801068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency' [patent_app_type] => B2 [patent_app_number] => 10/278888 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 11852 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801068.pdf [firstpage_image] =>[orig_patent_app_number] => 10278888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278888
Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency Oct 23, 2002 Issued
Array ( [id] => 1103157 [patent_doc_number] => 06815987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Phase locked loop' [patent_app_type] => B2 [patent_app_number] => 10/279102 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4510 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815987.pdf [firstpage_image] =>[orig_patent_app_number] => 10279102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279102
Phase locked loop Oct 23, 2002 Issued
Array ( [id] => 7160894 [patent_doc_number] => 20040075479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Reducing power and area consumption of gated clock enabled flip flops' [patent_app_type] => new [patent_app_number] => 10/274923 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4914 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075479.pdf [firstpage_image] =>[orig_patent_app_number] => 10274923 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274923
Reducing power and area consumption of gated clock enabled flip flops Oct 21, 2002 Issued
Array ( [id] => 788471 [patent_doc_number] => 06987405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-17 [patent_title] => 'Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors' [patent_app_type] => utility [patent_app_number] => 10/274424 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3745 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987405.pdf [firstpage_image] =>[orig_patent_app_number] => 10274424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274424
Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors Oct 17, 2002 Issued
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