
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7626398
[patent_doc_number] => 06768365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-27
[patent_title] => 'Low power reduced voltage swing latch'
[patent_app_type] => B2
[patent_app_number] => 10/274191
[patent_app_country] => US
[patent_app_date] => 2002-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1148
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/768/06768365.pdf
[firstpage_image] =>[orig_patent_app_number] => 10274191
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/274191 | Low power reduced voltage swing latch | Oct 17, 2002 | Issued |
Array
(
[id] => 7621963
[patent_doc_number] => 06977538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-20
[patent_title] => 'Delay unit for periodic signals'
[patent_app_type] => utility
[patent_app_number] => 10/273950
[patent_app_country] => US
[patent_app_date] => 2002-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3010
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/977/06977538.pdf
[firstpage_image] =>[orig_patent_app_number] => 10273950
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/273950 | Delay unit for periodic signals | Oct 17, 2002 | Issued |
Array
(
[id] => 6786095
[patent_doc_number] => 20030137334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Clock generator'
[patent_app_type] => new
[patent_app_number] => 10/271553
[patent_app_country] => US
[patent_app_date] => 2002-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4940
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20030137334.pdf
[firstpage_image] =>[orig_patent_app_number] => 10271553
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/271553 | Clock generator | Oct 16, 2002 | Issued |
Array
(
[id] => 6699813
[patent_doc_number] => 20030222693
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-04
[patent_title] => 'Variable delay generator'
[patent_app_type] => new
[patent_app_number] => 10/169261
[patent_app_country] => US
[patent_app_date] => 2002-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4126
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20030222693.pdf
[firstpage_image] =>[orig_patent_app_number] => 10169261
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/169261 | Variable delay generator | Oct 16, 2002 | Abandoned |
Array
(
[id] => 7163402
[patent_doc_number] => 20040076189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Multiphase clocking method and apparatus'
[patent_app_type] => new
[patent_app_number] => 10/273641
[patent_app_country] => US
[patent_app_date] => 2002-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1563
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20040076189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10273641
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/273641 | Multiphase clocking method and apparatus | Oct 16, 2002 | Abandoned |
Array
(
[id] => 7160899
[patent_doc_number] => 20040075481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Digitally-programmable delay line for multi-phase clock generator'
[patent_app_type] => new
[patent_app_number] => 10/271919
[patent_app_country] => US
[patent_app_date] => 2002-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7187
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20040075481.pdf
[firstpage_image] =>[orig_patent_app_number] => 10271919
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/271919 | Digitally-programmable delay line for multi-phase clock generator | Oct 15, 2002 | Issued |
Array
(
[id] => 1006399
[patent_doc_number] => 06906566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Dual-phase delay-locked loop circuit and method'
[patent_app_type] => utility
[patent_app_number] => 10/269398
[patent_app_country] => US
[patent_app_date] => 2002-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6952
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/906/06906566.pdf
[firstpage_image] =>[orig_patent_app_number] => 10269398
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269398 | Dual-phase delay-locked loop circuit and method | Oct 9, 2002 | Issued |
Array
(
[id] => 7436402
[patent_doc_number] => 20040066223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-08
[patent_title] => 'Balanced programmable delay element'
[patent_app_type] => new
[patent_app_number] => 10/266968
[patent_app_country] => US
[patent_app_date] => 2002-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3974
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20040066223.pdf
[firstpage_image] =>[orig_patent_app_number] => 10266968
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/266968 | Balanced programmable delay element | Oct 6, 2002 | Issued |
Array
(
[id] => 1185033
[patent_doc_number] => 06748575
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-08
[patent_title] => 'Programming programmable logic devices using hidden switches'
[patent_app_type] => B1
[patent_app_number] => 10/263251
[patent_app_country] => US
[patent_app_date] => 2002-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3418
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/748/06748575.pdf
[firstpage_image] =>[orig_patent_app_number] => 10263251
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263251 | Programming programmable logic devices using hidden switches | Oct 1, 2002 | Issued |
Array
(
[id] => 6748428
[patent_doc_number] => 20030042948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'PLL circuit'
[patent_app_type] => new
[patent_app_number] => 10/262191
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 19612
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20030042948.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262191
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262191 | Phase locked loop circuit having main and auxiliary frequency dividers and multiple phase comparisons | Sep 30, 2002 | Issued |
Array
(
[id] => 956659
[patent_doc_number] => 06956413
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'Ramp generator for image sensor ADC'
[patent_app_type] => utility
[patent_app_number] => 10/254443
[patent_app_country] => US
[patent_app_date] => 2002-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1843
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/956/06956413.pdf
[firstpage_image] =>[orig_patent_app_number] => 10254443
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/254443 | Ramp generator for image sensor ADC | Sep 24, 2002 | Issued |
Array
(
[id] => 1233073
[patent_doc_number] => 06693472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-17
[patent_title] => 'Method and circuit for adjusting the timing of output data based on an operational mode of output drivers'
[patent_app_type] => B2
[patent_app_number] => 10/243279
[patent_app_country] => US
[patent_app_date] => 2002-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8398
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/693/06693472.pdf
[firstpage_image] =>[orig_patent_app_number] => 10243279
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/243279 | Method and circuit for adjusting the timing of output data based on an operational mode of output drivers | Sep 11, 2002 | Issued |
Array
(
[id] => 1307328
[patent_doc_number] => 06621317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-16
[patent_title] => 'Clock controlling method and circuit'
[patent_app_type] => B2
[patent_app_number] => 10/237713
[patent_app_country] => US
[patent_app_date] => 2002-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 32
[patent_no_of_words] => 14157
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/621/06621317.pdf
[firstpage_image] =>[orig_patent_app_number] => 10237713
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/237713 | Clock controlling method and circuit | Sep 8, 2002 | Issued |
Array
(
[id] => 6681327
[patent_doc_number] => 20030117191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Clock synchronization circuit'
[patent_app_type] => new
[patent_app_number] => 10/236287
[patent_app_country] => US
[patent_app_date] => 2002-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5176
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20030117191.pdf
[firstpage_image] =>[orig_patent_app_number] => 10236287
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/236287 | Clock synchronization circuit | Sep 5, 2002 | Issued |
Array
(
[id] => 6748429
[patent_doc_number] => 20030042949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Current-steering charge pump circuit and method of switching'
[patent_app_type] => new
[patent_app_number] => 10/233862
[patent_app_country] => US
[patent_app_date] => 2002-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2329
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20030042949.pdf
[firstpage_image] =>[orig_patent_app_number] => 10233862
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233862 | Current-steering charge pump circuit and method of switching | Sep 2, 2002 | Issued |
Array
(
[id] => 1154524
[patent_doc_number] => 06771102
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-03
[patent_title] => 'Common mode feedback technique for a low voltage charge pump'
[patent_app_type] => B2
[patent_app_number] => 10/231601
[patent_app_country] => US
[patent_app_date] => 2002-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2263
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/771/06771102.pdf
[firstpage_image] =>[orig_patent_app_number] => 10231601
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/231601 | Common mode feedback technique for a low voltage charge pump | Aug 29, 2002 | Issued |
Array
(
[id] => 7130577
[patent_doc_number] => 20040041606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'SYNCHRONOUS MIRROR DELAY (SMD) CIRCUIT AND METHOD INCLUDING A RING OSCILLATOR FOR TIMING COARSE AND FINE DELAY INTERVALS'
[patent_app_type] => new
[patent_app_number] => 10/232475
[patent_app_country] => US
[patent_app_date] => 2002-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10423
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20040041606.pdf
[firstpage_image] =>[orig_patent_app_number] => 10232475
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232475 | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals | Aug 28, 2002 | Issued |
Array
(
[id] => 6748427
[patent_doc_number] => 20030042947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Frequency-doubling delay locked loop'
[patent_app_type] => new
[patent_app_number] => 10/227547
[patent_app_country] => US
[patent_app_date] => 2002-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5056
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20030042947.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227547
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227547 | Frequency-doubling delay locked loop | Aug 25, 2002 | Issued |
Array
(
[id] => 1354419
[patent_doc_number] => 06583656
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Differential clock driver with transmission-gate feedback to reduce voltage-crossing sensitivity to input skew'
[patent_app_type] => B1
[patent_app_number] => 10/064831
[patent_app_country] => US
[patent_app_date] => 2002-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3093
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/583/06583656.pdf
[firstpage_image] =>[orig_patent_app_number] => 10064831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064831 | Differential clock driver with transmission-gate feedback to reduce voltage-crossing sensitivity to input skew | Aug 20, 2002 | Issued |
Array
(
[id] => 1211353
[patent_doc_number] => 06714063
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-30
[patent_title] => 'Current pulse receiving circuit'
[patent_app_type] => B2
[patent_app_number] => 10/214149
[patent_app_country] => US
[patent_app_date] => 2002-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 15417
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/714/06714063.pdf
[firstpage_image] =>[orig_patent_app_number] => 10214149
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/214149 | Current pulse receiving circuit | Aug 7, 2002 | Issued |