Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1109610 [patent_doc_number] => 06809564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Clock generator for an integrated circuit with a high-speed serial interface' [patent_app_type] => B2 [patent_app_number] => 10/197061 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2637 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809564.pdf [firstpage_image] =>[orig_patent_app_number] => 10197061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197061
Clock generator for an integrated circuit with a high-speed serial interface Jul 16, 2002 Issued
Array ( [id] => 712768 [patent_doc_number] => 07057453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'Method and system for reducing parasitic feedback and parasitic resonances in high-gain transimpedance amplifiers' [patent_app_type] => utility [patent_app_number] => 10/198392 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1687 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057453.pdf [firstpage_image] =>[orig_patent_app_number] => 10198392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/198392
Method and system for reducing parasitic feedback and parasitic resonances in high-gain transimpedance amplifiers Jul 15, 2002 Issued
Array ( [id] => 6733802 [patent_doc_number] => 20030011437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => new [patent_app_number] => 10/197650 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9228 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20030011437.pdf [firstpage_image] =>[orig_patent_app_number] => 10197650 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197650
Phase locked loop circuit Jul 15, 2002 Issued
Array ( [id] => 5838927 [patent_doc_number] => 20060119407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Timing delay generator and method using temperature stabilisation' [patent_app_type] => utility [patent_app_number] => 10/090815 [patent_app_country] => US [patent_app_date] => 2002-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1390 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119407.pdf [firstpage_image] =>[orig_patent_app_number] => 10090815 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/090815
Timing delay generator and method using temperature stabilisation Jul 10, 2002 Issued
Array ( [id] => 1182887 [patent_doc_number] => 06741109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Method and apparatus for switching between input clocks in a phase-locked loop' [patent_app_type] => B1 [patent_app_number] => 10/187935 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 12592 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741109.pdf [firstpage_image] =>[orig_patent_app_number] => 10187935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/187935
Method and apparatus for switching between input clocks in a phase-locked loop Jul 1, 2002 Issued
Array ( [id] => 7422735 [patent_doc_number] => 20040000935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'DIGITAL CLOCK RATE MULTIPLIER METHOD AND APPARATUS' [patent_app_type] => new [patent_app_number] => 10/185618 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5575 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20040000935.pdf [firstpage_image] =>[orig_patent_app_number] => 10185618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185618
Digital clock rate multiplier method and apparatus Jun 27, 2002 Issued
Array ( [id] => 6790399 [patent_doc_number] => 20030085743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => new [patent_app_number] => 10/185147 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3455 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20030085743.pdf [firstpage_image] =>[orig_patent_app_number] => 10185147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185147
Phase locked loop circuit Jun 26, 2002 Abandoned
Array ( [id] => 1282273 [patent_doc_number] => 06646488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Delay circuit with delay relatively independent of process, voltage, and temperature variations' [patent_app_type] => B2 [patent_app_number] => 10/180501 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4527 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646488.pdf [firstpage_image] =>[orig_patent_app_number] => 10180501 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180501
Delay circuit with delay relatively independent of process, voltage, and temperature variations Jun 26, 2002 Issued
Array ( [id] => 1342079 [patent_doc_number] => 06593786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Register controlled DLL reducing current consumption' [patent_app_type] => B2 [patent_app_number] => 10/180528 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3980 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593786.pdf [firstpage_image] =>[orig_patent_app_number] => 10180528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180528
Register controlled DLL reducing current consumption Jun 26, 2002 Issued
Array ( [id] => 1367188 [patent_doc_number] => 06573769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Phase-locked loop (PLL) with mixer for subtracting outer-band phase noise' [patent_app_type] => B1 [patent_app_number] => 10/064271 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573769.pdf [firstpage_image] =>[orig_patent_app_number] => 10064271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064271
Phase-locked loop (PLL) with mixer for subtracting outer-band phase noise Jun 26, 2002 Issued
Array ( [id] => 7422746 [patent_doc_number] => 20040000936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Digital summing phase-lock loop circuit with sideband control and method therefor' [patent_app_type] => new [patent_app_number] => 10/183281 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2802 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20040000936.pdf [firstpage_image] =>[orig_patent_app_number] => 10183281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183281
Digital summing phase-lock loop circuit with sideband control and method therefor Jun 25, 2002 Issued
Array ( [id] => 1117284 [patent_doc_number] => 06801073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'System, circuit and method for low voltage operable, small footprint delay' [patent_app_type] => B2 [patent_app_number] => 10/179606 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4250 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801073.pdf [firstpage_image] =>[orig_patent_app_number] => 10179606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179606
System, circuit and method for low voltage operable, small footprint delay Jun 24, 2002 Issued
Array ( [id] => 1349154 [patent_doc_number] => 06586978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Delay locked loop' [patent_app_type] => B2 [patent_app_number] => 10/177945 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5603 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586978.pdf [firstpage_image] =>[orig_patent_app_number] => 10177945 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177945
Delay locked loop Jun 19, 2002 Issued
Array ( [id] => 1354439 [patent_doc_number] => 06583657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits' [patent_app_type] => B1 [patent_app_number] => 10/177391 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6245 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583657.pdf [firstpage_image] =>[orig_patent_app_number] => 10177391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177391
Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits Jun 19, 2002 Issued
Array ( [id] => 1267076 [patent_doc_number] => 06661262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Frequency doubling two-phase clock generation circuit' [patent_app_type] => B1 [patent_app_number] => 10/177323 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1737 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661262.pdf [firstpage_image] =>[orig_patent_app_number] => 10177323 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177323
Frequency doubling two-phase clock generation circuit Jun 19, 2002 Issued
Array ( [id] => 6321200 [patent_doc_number] => 20020196710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Switchable clock source' [patent_app_type] => new [patent_app_number] => 10/157731 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2067 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196710.pdf [firstpage_image] =>[orig_patent_app_number] => 10157731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157731
Switchable clock source May 28, 2002 Issued
Array ( [id] => 7284031 [patent_doc_number] => 20040145422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Frequency locked loop, clock recovery circuit and receiver' [patent_app_type] => new [patent_app_number] => 10/479095 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2328 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145422.pdf [firstpage_image] =>[orig_patent_app_number] => 10479095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/479095
Frequency locked loop, clock recovery circuit and receiver May 26, 2002 Issued
Array ( [id] => 6389225 [patent_doc_number] => 20020180547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Efficient pulse amplitude modulation transmit modulation' [patent_app_type] => new [patent_app_number] => 10/154093 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3370 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20020180547.pdf [firstpage_image] =>[orig_patent_app_number] => 10154093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154093
Efficient pulse amplitude modulation transmit modulation May 21, 2002 Issued
Array ( [id] => 6255690 [patent_doc_number] => 20020186064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Delay circuit having low operating environment dependency' [patent_app_type] => new [patent_app_number] => 10/150156 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 28478 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20020186064.pdf [firstpage_image] =>[orig_patent_app_number] => 10150156 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/150156
Delay circuit having low operating environment dependency May 19, 2002 Abandoned
Array ( [id] => 6753905 [patent_doc_number] => 20030001681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method and device for improving efficiency of frequency synthesizer' [patent_app_type] => new [patent_app_number] => 10/150600 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001681.pdf [firstpage_image] =>[orig_patent_app_number] => 10150600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/150600
Method and device for improving efficiency of frequency synthesizer May 16, 2002 Issued
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