Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1173237 [patent_doc_number] => 06753740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop' [patent_app_type] => B2 [patent_app_number] => 10/147593 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6075 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753740.pdf [firstpage_image] =>[orig_patent_app_number] => 10147593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/147593
Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop May 16, 2002 Issued
Array ( [id] => 6107876 [patent_doc_number] => 20020171473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Active common mode filter connected in A-C line' [patent_app_type] => new [patent_app_number] => 10/146334 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171473.pdf [firstpage_image] =>[orig_patent_app_number] => 10146334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146334
Active common mode filter connected in A-C line May 14, 2002 Issued
Array ( [id] => 999998 [patent_doc_number] => 06911850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/312882 [patent_app_country] => US [patent_app_date] => 2002-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6580 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911850.pdf [firstpage_image] =>[orig_patent_app_number] => 10312882 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/312882
Semiconductor integrated circuit May 13, 2002 Issued
Array ( [id] => 1152272 [patent_doc_number] => 06774739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Frequency converter, orthogonal demodulator and orthogonal modulator' [patent_app_type] => B2 [patent_app_number] => 10/141977 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5749 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774739.pdf [firstpage_image] =>[orig_patent_app_number] => 10141977 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/141977
Frequency converter, orthogonal demodulator and orthogonal modulator May 9, 2002 Issued
Array ( [id] => 1502876 [patent_doc_number] => 06486723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Programmable differential delay circuit with fine delay adjustment' [patent_app_type] => B1 [patent_app_number] => 10/142472 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4416 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 478 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486723.pdf [firstpage_image] =>[orig_patent_app_number] => 10142472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/142472
Programmable differential delay circuit with fine delay adjustment May 8, 2002 Issued
Array ( [id] => 7627652 [patent_doc_number] => 06806786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Phase-locked loop with self-selecting multi-band VCO' [patent_app_type] => B1 [patent_app_number] => 10/143529 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6236 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806786.pdf [firstpage_image] =>[orig_patent_app_number] => 10143529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/143529
Phase-locked loop with self-selecting multi-band VCO May 8, 2002 Issued
Array ( [id] => 1289805 [patent_doc_number] => 06639476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Correlator stabilized digitally tuned oscillator synthesizer' [patent_app_type] => B1 [patent_app_number] => 10/139810 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639476.pdf [firstpage_image] =>[orig_patent_app_number] => 10139810 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139810
Correlator stabilized digitally tuned oscillator synthesizer May 6, 2002 Issued
Array ( [id] => 1289840 [patent_doc_number] => 06639483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Pulse width modulation integrated circuit chip' [patent_app_type] => B2 [patent_app_number] => 10/139570 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3105 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639483.pdf [firstpage_image] =>[orig_patent_app_number] => 10139570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139570
Pulse width modulation integrated circuit chip May 5, 2002 Issued
Array ( [id] => 6807597 [patent_doc_number] => 20030197536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'METHOD AND APPARATUS FOR SYNTHESIZING A CLOCK SIGNAL USING A COMPACT AND LOW POWER DELAY LOCKED LOOP (DLL)' [patent_app_type] => new [patent_app_number] => 10/128325 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2364 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197536.pdf [firstpage_image] =>[orig_patent_app_number] => 10128325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/128325
Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL) Apr 22, 2002 Issued
Array ( [id] => 643184 [patent_doc_number] => 07123072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'High-accuracy capacitor digital-to-analog converter' [patent_app_type] => utility [patent_app_number] => 10/128663 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123072.pdf [firstpage_image] =>[orig_patent_app_number] => 10128663 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/128663
High-accuracy capacitor digital-to-analog converter Apr 22, 2002 Issued
Array ( [id] => 1303514 [patent_doc_number] => 06624674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method and apparatus for reducing variations on damping factor and natural frequency in phase locked loops' [patent_app_type] => B1 [patent_app_number] => 10/127574 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4520 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624674.pdf [firstpage_image] =>[orig_patent_app_number] => 10127574 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127574
Method and apparatus for reducing variations on damping factor and natural frequency in phase locked loops Apr 22, 2002 Issued
Array ( [id] => 1022854 [patent_doc_number] => 06888386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method and apparatus for change pump circuit' [patent_app_type] => utility [patent_app_number] => 10/127732 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3288 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888386.pdf [firstpage_image] =>[orig_patent_app_number] => 10127732 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127732
Method and apparatus for change pump circuit Apr 22, 2002 Issued
Array ( [id] => 1289636 [patent_doc_number] => 06639443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Conditional clock buffer circuit' [patent_app_type] => B1 [patent_app_number] => 10/127103 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17181 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639443.pdf [firstpage_image] =>[orig_patent_app_number] => 10127103 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127103
Conditional clock buffer circuit Apr 21, 2002 Issued
Array ( [id] => 7630847 [patent_doc_number] => 06636085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Phase shifter with an RC polyphase filter' [patent_app_type] => B2 [patent_app_number] => 10/125826 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8994 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636085.pdf [firstpage_image] =>[orig_patent_app_number] => 10125826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125826
Phase shifter with an RC polyphase filter Apr 18, 2002 Issued
Array ( [id] => 6807599 [patent_doc_number] => 20030197538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of performing duty cycle correction' [patent_app_type] => new [patent_app_number] => 10/126036 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3703 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197538.pdf [firstpage_image] =>[orig_patent_app_number] => 10126036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/126036
Method of performing duty cycle correction Apr 17, 2002 Issued
Array ( [id] => 1226219 [patent_doc_number] => 06700420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Differential output structure with reduced skew for a single input' [patent_app_type] => B2 [patent_app_number] => 10/125963 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 2564 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700420.pdf [firstpage_image] =>[orig_patent_app_number] => 10125963 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125963
Differential output structure with reduced skew for a single input Apr 17, 2002 Issued
Array ( [id] => 1103168 [patent_doc_number] => 06815993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => '/2 phase shifter' [patent_app_type] => B1 [patent_app_number] => 10/110203 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815993.pdf [firstpage_image] =>[orig_patent_app_number] => 10110203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/110203
/2 phase shifter Apr 16, 2002 Issued
Array ( [id] => 6447928 [patent_doc_number] => 20020149406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Timing adjusting circuit' [patent_app_type] => new [patent_app_number] => 10/124133 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2255 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149406.pdf [firstpage_image] =>[orig_patent_app_number] => 10124133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/124133
Timing adjusting circuit Apr 16, 2002 Issued
Array ( [id] => 6171242 [patent_doc_number] => 20020153932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Programmable delay for processor control signals' [patent_app_type] => new [patent_app_number] => 10/124673 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2618 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20020153932.pdf [firstpage_image] =>[orig_patent_app_number] => 10124673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/124673
Programmable delay for processor control signals Apr 16, 2002 Issued
Array ( [id] => 7623384 [patent_doc_number] => 06686781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Timing control circuit' [patent_app_type] => B2 [patent_app_number] => 10/121796 [patent_app_country] => US [patent_app_date] => 2002-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1167 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686781.pdf [firstpage_image] =>[orig_patent_app_number] => 10121796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/121796
Timing control circuit Apr 11, 2002 Issued
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