
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 549940
[patent_doc_number] => 07164310
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-01-16
[patent_title] => 'Systems and apparatus for digital control of bias for transistors'
[patent_app_type] => utility
[patent_app_number] => 10/121570
[patent_app_country] => US
[patent_app_date] => 2002-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6639
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/164/07164310.pdf
[firstpage_image] =>[orig_patent_app_number] => 10121570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/121570 | Systems and apparatus for digital control of bias for transistors | Apr 11, 2002 | Issued |
Array
(
[id] => 1181279
[patent_doc_number] => 06744293
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-01
[patent_title] => 'Global clock tree de-skew'
[patent_app_type] => B1
[patent_app_number] => 10/120576
[patent_app_country] => US
[patent_app_date] => 2002-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2168
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/744/06744293.pdf
[firstpage_image] =>[orig_patent_app_number] => 10120576
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/120576 | Global clock tree de-skew | Apr 8, 2002 | Issued |
Array
(
[id] => 1097996
[patent_doc_number] => 06822483
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'No resonance mode bang-bang phase detector'
[patent_app_type] => B1
[patent_app_number] => 10/121013
[patent_app_country] => US
[patent_app_date] => 2002-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1832
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/822/06822483.pdf
[firstpage_image] =>[orig_patent_app_number] => 10121013
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/121013 | No resonance mode bang-bang phase detector | Apr 8, 2002 | Issued |
Array
(
[id] => 6863929
[patent_doc_number] => 20030189455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'CMOS transmission gate with high impedance at power off'
[patent_app_type] => new
[patent_app_number] => 10/119101
[patent_app_country] => US
[patent_app_date] => 2002-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2838
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20030189455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10119101
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/119101 | CMOS transmission gate with high impedance at power off | Apr 7, 2002 | Issued |
Array
(
[id] => 6540286
[patent_doc_number] => 20020163392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-07
[patent_title] => 'Digital circuit for, and a method of, synthesizing an input signal'
[patent_app_type] => new
[patent_app_number] => 10/118200
[patent_app_country] => US
[patent_app_date] => 2002-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3555
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20020163392.pdf
[firstpage_image] =>[orig_patent_app_number] => 10118200
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/118200 | Digital circuit for, and a method of, synthesizing an input signal | Apr 4, 2002 | Issued |
Array
(
[id] => 1083904
[patent_doc_number] => 06833775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-21
[patent_title] => 'Microwave circuit'
[patent_app_type] => B2
[patent_app_number] => 10/114498
[patent_app_country] => US
[patent_app_date] => 2002-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1635
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/833/06833775.pdf
[firstpage_image] =>[orig_patent_app_number] => 10114498
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/114498 | Microwave circuit | Apr 1, 2002 | Issued |
Array
(
[id] => 6270819
[patent_doc_number] => 20020105366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-08
[patent_title] => 'PROCESS, VOLTAGE AND TEMPERATURE INDEPENDENT CLOCK TREE DESKEW CIRCUITRY -TEMPORARY DRIVER METHOD'
[patent_app_type] => new
[patent_app_number] => 10/109974
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5444
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20020105366.pdf
[firstpage_image] =>[orig_patent_app_number] => 10109974
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/109974 | Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method | Mar 28, 2002 | Issued |
Array
(
[id] => 6728166
[patent_doc_number] => 20030184356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'METHOD AND APPARATUS FOR PRECISE SIGNAL INTERPOLATION'
[patent_app_type] => new
[patent_app_number] => 10/112638
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7920
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20030184356.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112638
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112638 | Method and apparatus for precise signal interpolation | Mar 28, 2002 | Issued |
Array
(
[id] => 5901846
[patent_doc_number] => 20020140411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Device for recognizing power sources and associated method'
[patent_app_type] => new
[patent_app_number] => 10/108862
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3009
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20020140411.pdf
[firstpage_image] =>[orig_patent_app_number] => 10108862
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/108862 | Device for recognizing power sources and associated method | Mar 28, 2002 | Issued |
Array
(
[id] => 1403279
[patent_doc_number] => 06545519
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Level shifting, scannable latch, and method therefor'
[patent_app_type] => B1
[patent_app_number] => 10/112487
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3214
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/545/06545519.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112487
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112487 | Level shifting, scannable latch, and method therefor | Mar 27, 2002 | Issued |
Array
(
[id] => 5901913
[patent_doc_number] => 20020140462
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Semiconductor circuit'
[patent_app_type] => new
[patent_app_number] => 10/107324
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2536
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20020140462.pdf
[firstpage_image] =>[orig_patent_app_number] => 10107324
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/107324 | Semiconductor circuit | Mar 27, 2002 | Issued |
Array
(
[id] => 1257779
[patent_doc_number] => 06667640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-23
[patent_title] => 'Phase locked loop circuit having a wide oscillation frequency range for reducing jitter'
[patent_app_type] => B2
[patent_app_number] => 10/106257
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 9150
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/667/06667640.pdf
[firstpage_image] =>[orig_patent_app_number] => 10106257
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/106257 | Phase locked loop circuit having a wide oscillation frequency range for reducing jitter | Mar 26, 2002 | Issued |
Array
(
[id] => 5901933
[patent_doc_number] => 20020140472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/108007
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9614
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20020140472.pdf
[firstpage_image] =>[orig_patent_app_number] => 10108007
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/108007 | Semiconductor device for clock signals synchronization accuracy | Mar 26, 2002 | Issued |
Array
(
[id] => 1387631
[patent_doc_number] => 06559696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal'
[patent_app_type] => B1
[patent_app_number] => 10/089180
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3934
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/559/06559696.pdf
[firstpage_image] =>[orig_patent_app_number] => 10089180
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/089180 | Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal | Mar 26, 2002 | Issued |
Array
(
[id] => 6107845
[patent_doc_number] => 20020171458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Odd -number factor frequency divider and 90o phase splitter which operates from output signal of the frequency divider'
[patent_app_type] => new
[patent_app_number] => 10/103868
[patent_app_country] => US
[patent_app_date] => 2002-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4404
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20020171458.pdf
[firstpage_image] =>[orig_patent_app_number] => 10103868
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/103868 | Odd -number factor frequency divider and 90o phase splitter which operates from output signal of the frequency divider | Mar 24, 2002 | Abandoned |
Array
(
[id] => 6827969
[patent_doc_number] => 20030179027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Locked loop with dual rail regulation'
[patent_app_type] => new
[patent_app_number] => 10/104230
[patent_app_country] => US
[patent_app_date] => 2002-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 17718
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20030179027.pdf
[firstpage_image] =>[orig_patent_app_number] => 10104230
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/104230 | Locked loop with dual rail regulation | Mar 21, 2002 | Issued |
Array
(
[id] => 6831537
[patent_doc_number] => 20030182595
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)'
[patent_app_type] => new
[patent_app_number] => 10/102274
[patent_app_country] => US
[patent_app_date] => 2002-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6747
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20030182595.pdf
[firstpage_image] =>[orig_patent_app_number] => 10102274
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/102274 | Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs) | Mar 19, 2002 | Issued |
Array
(
[id] => 6827968
[patent_doc_number] => 20030179026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Delay lock loop having a variable voltage regulator'
[patent_app_type] => new
[patent_app_number] => 10/100713
[patent_app_country] => US
[patent_app_date] => 2002-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4793
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20030179026.pdf
[firstpage_image] =>[orig_patent_app_number] => 10100713
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/100713 | Delay lock loop having a variable voltage regulator | Mar 18, 2002 | Issued |
Array
(
[id] => 1146137
[patent_doc_number] => 06777990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-17
[patent_title] => 'Delay lock loop having an edge detector and fixed delay'
[patent_app_type] => B2
[patent_app_number] => 10/100639
[patent_app_country] => US
[patent_app_date] => 2002-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5302
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/777/06777990.pdf
[firstpage_image] =>[orig_patent_app_number] => 10100639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/100639 | Delay lock loop having an edge detector and fixed delay | Mar 18, 2002 | Issued |
Array
(
[id] => 6107850
[patent_doc_number] => 20020171460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Sinusoidal signal multiplier circuit'
[patent_app_type] => new
[patent_app_number] => 10/101561
[patent_app_country] => US
[patent_app_date] => 2002-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 990
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20020171460.pdf
[firstpage_image] =>[orig_patent_app_number] => 10101561
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/101561 | Sinusoidal signal multiplier circuit | Mar 18, 2002 | Issued |