Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1410059 [patent_doc_number] => 06538484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'High-frequency PWM voltage control' [patent_app_type] => B1 [patent_app_number] => 10/100273 [patent_app_country] => US [patent_app_date] => 2002-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5782 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538484.pdf [firstpage_image] =>[orig_patent_app_number] => 10100273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100273
High-frequency PWM voltage control Mar 17, 2002 Issued
Array ( [id] => 6154696 [patent_doc_number] => 20020145456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Multiplied clock generating circuit' [patent_app_type] => new [patent_app_number] => 10/097430 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13360 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145456.pdf [firstpage_image] =>[orig_patent_app_number] => 10097430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097430
Multiplied clock generating circuit Mar 14, 2002 Issued
Array ( [id] => 1285518 [patent_doc_number] => 06642747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Frequency detector for a phase locked loop system' [patent_app_type] => B1 [patent_app_number] => 10/099529 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5592 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642747.pdf [firstpage_image] =>[orig_patent_app_number] => 10099529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099529
Frequency detector for a phase locked loop system Mar 14, 2002 Issued
Array ( [id] => 6743339 [patent_doc_number] => 20030020522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Digital frequency divider' [patent_app_type] => new [patent_app_number] => 10/099588 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3212 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20030020522.pdf [firstpage_image] =>[orig_patent_app_number] => 10099588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099588
Digital frequency divider with a single shift register Mar 12, 2002 Issued
Array ( [id] => 6076801 [patent_doc_number] => 20020079958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Signal processing semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/087820 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11525 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079958.pdf [firstpage_image] =>[orig_patent_app_number] => 10087820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087820
Signal processing semiconductor integrated circuit device Mar 4, 2002 Issued
Array ( [id] => 1246933 [patent_doc_number] => 06677786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Multi-service processor clocking system' [patent_app_type] => B2 [patent_app_number] => 10/086500 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3971 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677786.pdf [firstpage_image] =>[orig_patent_app_number] => 10086500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/086500
Multi-service processor clocking system Feb 27, 2002 Issued
Array ( [id] => 7963593 [patent_doc_number] => 06680632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method/architecture for a low gain PLL with wide frequency range' [patent_app_type] => B1 [patent_app_number] => 10/083442 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680632.pdf [firstpage_image] =>[orig_patent_app_number] => 10083442 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083442
Method/architecture for a low gain PLL with wide frequency range Feb 25, 2002 Issued
Array ( [id] => 5918717 [patent_doc_number] => 20020113637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Phase-interpolation circuit and a phase-interpolation signal generating device applying the same' [patent_app_type] => new [patent_app_number] => 10/079866 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5267 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113637.pdf [firstpage_image] =>[orig_patent_app_number] => 10079866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079866
Phase-interpolation circuit and a phase-interpolation signal generating device applying the same Feb 20, 2002 Issued
Array ( [id] => 6686750 [patent_doc_number] => 20030030473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Ring-resister controlled DLL with fine delay line and direct skew sensing detector' [patent_app_type] => new [patent_app_number] => 10/073358 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7802 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20030030473.pdf [firstpage_image] =>[orig_patent_app_number] => 10073358 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073358
Ring-resister controlled DLL with fine delay line and direct skew sensing detector Feb 12, 2002 Abandoned
Array ( [id] => 6714190 [patent_doc_number] => 20030025538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Loop filter architecture' [patent_app_type] => new [patent_app_number] => 10/072094 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1560 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025538.pdf [firstpage_image] =>[orig_patent_app_number] => 10072094 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/072094
Loop filter architecture Feb 7, 2002 Issued
Array ( [id] => 6270832 [patent_doc_number] => 20020105371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Inverter circuit' [patent_app_type] => new [patent_app_number] => 10/066819 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5176 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105371.pdf [firstpage_image] =>[orig_patent_app_number] => 10066819 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066819
Inverter circuit Feb 3, 2002 Abandoned
Array ( [id] => 6704707 [patent_doc_number] => 20030151441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Interleaved clock signal generator having serial delay and ring counter architecture' [patent_app_type] => new [patent_app_number] => 10/061504 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151441.pdf [firstpage_image] =>[orig_patent_app_number] => 10061504 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061504
Interleaved clock signal generator having serial delay and ring counter architecture Jan 31, 2002 Issued
Array ( [id] => 6014375 [patent_doc_number] => 20020101955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Fractional frequency division of a digital signal' [patent_app_type] => new [patent_app_number] => 10/062822 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4559 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20020101955.pdf [firstpage_image] =>[orig_patent_app_number] => 10062822 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062822
Fractional frequency division of a digital signal Jan 30, 2002 Issued
Array ( [id] => 1233170 [patent_doc_number] => 06693493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Single-ended differential circuit using complementary devices' [patent_app_type] => B2 [patent_app_number] => 10/051290 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6897 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693493.pdf [firstpage_image] =>[orig_patent_app_number] => 10051290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051290
Single-ended differential circuit using complementary devices Jan 21, 2002 Issued
Array ( [id] => 6076781 [patent_doc_number] => 20020079946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Gain controller using switched capacitors' [patent_app_type] => new [patent_app_number] => 10/044039 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5297 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079946.pdf [firstpage_image] =>[orig_patent_app_number] => 10044039 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044039
Gain controller using switched capacitors Jan 10, 2002 Issued
Array ( [id] => 1267109 [patent_doc_number] => 06661272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Digitally controllable internal clock generating circuit of semiconductor memory device and method for same' [patent_app_type] => B2 [patent_app_number] => 10/041060 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3032 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661272.pdf [firstpage_image] =>[orig_patent_app_number] => 10041060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041060
Digitally controllable internal clock generating circuit of semiconductor memory device and method for same Jan 6, 2002 Issued
Array ( [id] => 7149036 [patent_doc_number] => 20050024109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Skew delay compensator' [patent_app_type] => utility [patent_app_number] => 10/499602 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4738 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024109.pdf [firstpage_image] =>[orig_patent_app_number] => 10499602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/499602
Skew delay compensator Dec 19, 2001 Issued
Array ( [id] => 7301726 [patent_doc_number] => 20040113703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Phase-locked loop' [patent_app_type] => new [patent_app_number] => 10/466788 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113703.pdf [firstpage_image] =>[orig_patent_app_number] => 10466788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/466788
Phase-locked loop Dec 17, 2001 Issued
Array ( [id] => 1367260 [patent_doc_number] => 06573775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Integrated circuit flip-flops that utilize master and slave latched sense amplifiers' [patent_app_type] => B2 [patent_app_number] => 10/010847 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12169 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573775.pdf [firstpage_image] =>[orig_patent_app_number] => 10010847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010847
Integrated circuit flip-flops that utilize master and slave latched sense amplifiers Dec 4, 2001 Issued
Array ( [id] => 1060555 [patent_doc_number] => 06853230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method and apparatus for producing a clock output signal' [patent_app_type] => utility [patent_app_number] => 09/992281 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2879 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853230.pdf [firstpage_image] =>[orig_patent_app_number] => 09992281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992281
Method and apparatus for producing a clock output signal Nov 15, 2001 Issued
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